mirror of https://github.com/m-labs/artiq.git
sayma_amc: output ddmtd_rec_clk
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ae50da09c4
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@ -66,6 +66,10 @@ class SatelliteBase(MiniSoC):
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platform = self.platform
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if with_wrpll:
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clock_recout_pads = platform.request("ddmtd_rec_clk")
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else:
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clock_recout_pads = None
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# Use SFP0 to connect to master (Kasli)
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self.comb += platform.request("sfp_tx_disable", 0).eq(0)
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drtio_data_pads = [
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@ -76,7 +80,8 @@ class SatelliteBase(MiniSoC):
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clock_pads=platform.request("cdr_clk_clean"),
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data_pads=drtio_data_pads,
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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rtio_clk_freq=rtio_clk_freq,
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clock_recout_pads=clock_recout_pads)
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self.csr_devices.append("drtio_transceiver")
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self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
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