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https://github.com/m-labs/artiq.git
synced 2024-12-26 03:38:25 +08:00
Add Zotino and Sampler functions to Kasli. Add Zotino to Kasli EEM 7 on OptiClock.
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f39b7b33e8
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@ -161,6 +161,44 @@ def _dio(eem):
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for i in range(8)]
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for i in range(8)]
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def _sampler(eem):
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return [
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("{}_adc_spi_p".format(eem), 0,
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Subsignal("clk", Pins("{}:{}_p".format(eem, _eem_signal(0)))),
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Subsignal("miso", Pins("{}:{}_p".format(eem, _eem_signal(1)))),
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IOStandard("LVDS_25"),
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),
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("{}_adc_spi_n".format(eem), 0,
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Subsignal("clk", Pins("{}:{}_n".format(eem, _eem_signal(0)))),
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Subsignal("miso", Pins("{}:{}_n".format(eem, _eem_signal(1)))),
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IOStandard("LVDS_25"),
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),
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("{}_pgia_spi_p".format(eem), 0,
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Subsignal("clk", Pins("{}:{}_p".format(eem, _eem_signal(4)))),
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Subsignal("mosi", Pins("{}:{}_p".format(eem, _eem_signal(5)))),
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Subsignal("miso", Pins("{}:{}_p".format(eem, _eem_signal(6)))),
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Subsignal("cs_n", Pins("{}:{}_p".format(eem, _eem_signal(7)))),
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IOStandard("LVDS_25"),
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),
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("{}_pgia_spi_n".format(eem), 0,
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Subsignal("clk", Pins("{}:{}_n".format(eem, _eem_signal(4)))),
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Subsignal("mosi", Pins("{}:{}_n".format(eem, _eem_signal(5)))),
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Subsignal("miso", Pins("{}:{}_n".format(eem, _eem_signal(6)))),
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Subsignal("cs_n", Pins("{}:{}_n".format(eem, _eem_signal(7)))),
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IOStandard("LVDS_25"),
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),
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] + [
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("{}_{}".format(eem, sig), 0,
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Subsignal("p", Pins("{}:{}_p".format(j, _eem_signal(i)))),
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Subsignal("n", Pins("{}:{}_n".format(j, _eem_signal(i)))),
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IOStandard("LVDS_25")
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) for i, j, sig in [
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(2, eem, "cnv"),
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(3, eem, "sdr")
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]
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]
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def _novogorny(eem):
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def _novogorny(eem):
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return [
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return [
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("{}_spi_p".format(eem), 0,
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("{}_spi_p".format(eem), 0,
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@ -194,6 +232,39 @@ def _novogorny(eem):
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]
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]
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def _zotino(eem):
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return [
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("{}_spi_p".format(eem), 0,
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Subsignal("clk", Pins("{}:{}_p".format(eem, _eem_signal(0)))),
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Subsignal("mosi", Pins("{}:{}_p".format(eem, _eem_signal(1)))),
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Subsignal("miso", Pins("{}:{}_p".format(eem, _eem_signal(2)))),
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Subsignal("cs_n", Pins(
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"{0}:{1[0]}_p {0}:{1[1]}_p".format(
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eem, [_eem_signal(i + 3) for i in range(2)]))),
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IOStandard("LVDS_25"),
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),
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("{}_spi_n".format(eem), 0,
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Subsignal("clk", Pins("{}:{}_n".format(eem, _eem_signal(0)))),
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Subsignal("mosi", Pins("{}:{}_n".format(eem, _eem_signal(1)))),
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Subsignal("miso", Pins("{}:{}_n".format(eem, _eem_signal(2)))),
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Subsignal("cs_n", Pins(
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"{0}:{1[0]}_n {0}:{1[1]}_n".format(
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eem, [_eem_signal(i + 3) for i in range(2)]))),
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IOStandard("LVDS_25"),
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),
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] + [
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("{}_{}".format(eem, sig), 0,
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Subsignal("p", Pins("{}:{}_p".format(j, _eem_signal(i)))),
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Subsignal("n", Pins("{}:{}_n".format(j, _eem_signal(i)))),
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IOStandard("LVDS_25")
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) for i, j, sig in [
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(5, eem, "ldac_n"),
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(6, eem, "busy"),
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(7, eem, "clr_n"),
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]
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]
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def _urukul(eem, eem_aux=None):
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def _urukul(eem, eem_aux=None):
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ios = [
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ios = [
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("{}_spi_p".format(eem), 0,
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("{}_spi_p".format(eem), 0,
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@ -254,7 +325,7 @@ class Opticlock(_StandaloneBase):
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platform.add_extension(_novogorny("eem3"))
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platform.add_extension(_novogorny("eem3"))
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platform.add_extension(_urukul("eem5", "eem4"))
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platform.add_extension(_urukul("eem5", "eem4"))
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platform.add_extension(_urukul("eem6"))
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platform.add_extension(_urukul("eem6"))
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# platform.add_extension(_zotino("eem7"))
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platform.add_extension(_zotino("eem7"))
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# EEM clock fan-out from Si5324, not MMCX
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# EEM clock fan-out from Si5324, not MMCX
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try:
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try:
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@ -274,6 +345,7 @@ class Opticlock(_StandaloneBase):
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# EEM3: Novogorny
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phy = spi2.SPIMaster(self.platform.request("eem3_spi_p"),
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phy = spi2.SPIMaster(self.platform.request("eem3_spi_p"),
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self.platform.request("eem3_spi_n"))
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self.platform.request("eem3_spi_n"))
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self.submodules += phy
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self.submodules += phy
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@ -285,6 +357,7 @@ class Opticlock(_StandaloneBase):
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# EEM3 + EEM5: Urukul
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phy = spi2.SPIMaster(self.platform.request("eem5_spi_p"),
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phy = spi2.SPIMaster(self.platform.request("eem5_spi_p"),
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self.platform.request("eem5_spi_n"))
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self.platform.request("eem5_spi_n"))
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self.submodules += phy
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self.submodules += phy
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@ -305,6 +378,7 @@ class Opticlock(_StandaloneBase):
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# EEM6: Urukul
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phy = spi2.SPIMaster(self.platform.request("eem6_spi_p"),
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phy = spi2.SPIMaster(self.platform.request("eem6_spi_p"),
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self.platform.request("eem6_spi_n"))
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self.platform.request("eem6_spi_n"))
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self.submodules += phy
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self.submodules += phy
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@ -319,6 +393,18 @@ class Opticlock(_StandaloneBase):
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pads = platform.request("eem6_dds_reset")
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pads = platform.request("eem6_dds_reset")
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self.specials += DifferentialOutput(0, pads.p, pads.n)
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self.specials += DifferentialOutput(0, pads.p, pads.n)
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# EEM7: Zotino
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phy = spi2.SPIMaster(self.platform.request("eem7_spi_p"),
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self.platform.request("eem7_spi_n"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=16))
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for signal in "ldac_n clr_n".split():
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pads = platform.request("eem7_{}".format(signal))
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phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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rtio_channels.append(rtio.LogChannel())
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