2
0
mirror of https://github.com/m-labs/artiq.git synced 2024-12-28 20:53:35 +08:00

hmc7043: disable FPGA_ADC_SYSREF

This commit is contained in:
Sebastien Bourdeauducq 2018-08-18 11:42:57 +08:00
parent a7810502f6
commit c498b28f88

View File

@ -174,7 +174,7 @@ pub mod hmc7043 {
(true, FPGA_CLK_DIV, 0x08), // 8: GTP_CLK1
(false, 0, 0x10), // 9: AMC_MASTER_AUX_CLK
(false, 0, 0x10), // 10: RTM_MASTER_AUX_CLK
(true, FPGA_CLK_DIV, 0x10), // 11: FPGA_ADC_SYSREF, LVDS -- repurposed for siphaser
(false, 0, 0x10), // 11: FPGA_ADC_SYSREF, LVDS
(false, 0, 0x08), // 12: ADC1_CLK
(false, 0, 0x08), // 13: ADC1_SYSREF
];