mirror of https://github.com/m-labs/artiq.git
Kasli JSON description for SPI over DIO cards (#1800)
This commit is contained in:
Leon Riesebos
GitHub
parent
2b918ac6f7
commit
c4292770f8
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@ -33,6 +33,8 @@ Highlights:
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warning is logged. The warning is additional to the one already printed in the core device log upon
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detection of the error.
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* Removed worker DB warning for writing a dataset that is also in the archive
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* Extended Kasli gateware JSON description with configuration for SPI over DIO.
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See: https://github.com/m-labs/artiq/pull/1800
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Breaking changes:
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@ -134,7 +134,7 @@
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"properties": {
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"type": {
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"type": "string",
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"enum": ["dio", "urukul", "novogorny", "sampler", "suservo", "zotino", "grabber", "mirny", "fastino", "phaser", "hvamp"]
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"enum": ["dio", "dio_spi", "urukul", "novogorny", "sampler", "suservo", "zotino", "grabber", "mirny", "fastino", "phaser", "hvamp"]
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},
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"board": {
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"type": "string"
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@ -179,6 +179,89 @@
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},
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"required": ["ports", "bank_direction_low", "bank_direction_high"]
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}
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}, {
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"title": "DIO_SPI",
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"if": {
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"properties": {
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"type": {
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"const": "dio_spi"
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}
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}
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},
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"then": {
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"properties": {
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"ports": {
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"type": "array",
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"items": {
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"type": "integer"
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},
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"minItems": 1,
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"maxItems": 1
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},
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"spi": {
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"type": "array",
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"items": {
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"type": "object",
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"properties": {
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"name": {
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"type": "string"
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},
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"clk": {
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"type": "integer",
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"minimum": 0,
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"maximum": 7
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},
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"mosi": {
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"type": "integer",
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"minimum": 0,
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"maximum": 7
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},
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"miso": {
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"type": "integer",
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"minimum": 0,
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"maximum": 7
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},
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"cs": {
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"type": "array",
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"items": {
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"type": "integer",
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"minimum": 0,
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"maximum": 7
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}
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}
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},
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"required": ["clk"]
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},
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"minItems": 1
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},
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"ttl": {
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"type": "array",
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"items": {
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"type": "object",
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"properties": {
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"name": {
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"type": "string"
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},
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"pin": {
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"type": "integer",
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"minimum": 0,
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"maximum": 7
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},
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"direction": {
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"type": "string",
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"enum": ["input", "output"]
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},
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"edge_counter": {
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"type": "boolean",
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"default": false
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}
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},
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"required": ["pin", "direction"]
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}
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}
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},
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"required": ["ports", "spi"]
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}
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}, {
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"title": "Urukul",
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"if": {
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@ -102,8 +102,7 @@ class PeripheralManager:
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"module": "artiq.coredevice.ttl",
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"class": "{class_name}",
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"arguments": {{"channel": 0x{channel:06x}}},
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}}
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""",
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}}""",
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name=name[i],
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class_name=classes[i // 4],
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channel=rtio_offset + next(channel))
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@ -117,25 +116,64 @@ class PeripheralManager:
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"module": "artiq.coredevice.edge_counter",
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"class": "EdgeCounter",
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"arguments": {{"channel": 0x{channel:06x}}},
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}}
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""",
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}}""",
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name=name[i],
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channel=rtio_offset + next(channel))
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return next(channel)
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def process_dio_spi(self, rtio_offset, peripheral):
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channel = count(0)
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for spi in peripheral["spi"]:
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self.gen("""
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device_db["{name}"] = {{
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {{"channel": 0x{channel:06x}}}
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}}""",
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name=self.get_name(spi.get("name", "dio_spi")),
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channel=rtio_offset + next(channel))
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for ttl in peripheral.get("ttl", []):
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ttl_class_names = {
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"input": "TTLInOut",
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"output": "TTLOut"
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}
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name = self.get_name(ttl.get("name", "ttl"))
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self.gen("""
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device_db["{name}"] = {{
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "{class_name}",
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"arguments": {{"channel": 0x{channel:06x}}},
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}}""",
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name=name,
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class_name=ttl_class_names[ttl["direction"]],
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channel=rtio_offset + next(channel))
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if ttl.get("edge_counter", False):
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self.gen("""
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device_db["{name}_counter"] = {{
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"type": "local",
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"module": "artiq.coredevice.edge_counter",
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"class": "EdgeCounter",
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"arguments": {{"channel": 0x{channel:06x}}},
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}}""",
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name=name,
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channel=rtio_offset + next(channel))
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return next(channel)
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def process_urukul(self, rtio_offset, peripheral):
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urukul_name = self.get_name("urukul")
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synchronization = peripheral["synchronization"]
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channel = count(0)
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self.gen("""
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device_db["eeprom_{name}"]={{
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device_db["eeprom_{name}"] = {{
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"type": "local",
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"module": "artiq.coredevice.kasli_i2c",
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"class": "KasliEEPROM",
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"arguments": {{"port": "EEM{eem}"}}
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}}
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device_db["spi_{name}"]={{
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device_db["spi_{name}"] = {{
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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@ -70,6 +70,65 @@ class DIO(_EEM):
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target.rtio_channels.append(rtio.Channel.from_phy(counter))
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class DIO_SPI(_EEM):
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@staticmethod
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def io(eem, spi, ttl, iostandard):
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def spi_subsignals(clk, mosi, miso, cs, pol):
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signals = [Subsignal("clk", Pins(_eem_pin(eem, clk, pol)))]
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if mosi is not None:
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signals.append(Subsignal("mosi",
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Pins(_eem_pin(eem, mosi, pol))))
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if miso is not None:
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signals.append(Subsignal("miso",
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Pins(_eem_pin(eem, miso, pol))))
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if cs:
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signals.append(Subsignal("cs_n", Pins(
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*(_eem_pin(eem, pin, pol) for pin in cs))))
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return signals
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spi = [
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("dio{}_spi{}_{}".format(eem, i, pol), i,
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*spi_subsignals(clk, mosi, miso, cs, pol),
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iostandard(eem))
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for i, (clk, mosi, miso, cs) in enumerate(spi) for pol in "pn"
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]
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ttl = [
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("dio{}".format(eem), i,
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Subsignal("p", Pins(_eem_pin(eem, pin, "p"))),
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Subsignal("n", Pins(_eem_pin(eem, pin, "n"))),
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iostandard(eem))
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for i, (pin, _, _) in enumerate(ttl)
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]
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return spi + ttl
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@classmethod
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def add_std(cls, target, eem, spi, ttl, iostandard=default_iostandard):
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cls.add_extension(target, eem, spi, ttl, iostandard=iostandard)
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for i in range(len(spi)):
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phy = spi2.SPIMaster(
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target.platform.request("dio{}_spi{}_p".format(eem, i)),
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target.platform.request("dio{}_spi{}_n".format(eem, i))
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)
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target.submodules += phy
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target.rtio_channels.append(
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rtio.Channel.from_phy(phy, ififo_depth=4))
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dci = iostandard(eem).name == "LVDS"
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for i, (_, ttl_cls, edge_counter_cls) in enumerate(ttl):
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pads = target.platform.request("dio{}".format(eem), i)
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phy = ttl_cls(pads.p, pads.n, dci=dci)
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target.submodules += phy
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target.rtio_channels.append(rtio.Channel.from_phy(phy))
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if edge_counter_cls is not None:
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state = getattr(phy, "input_state", None)
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if state is not None:
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counter = edge_counter_cls(state)
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target.submodules += counter
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target.rtio_channels.append(rtio.Channel.from_phy(counter))
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class Urukul(_EEM):
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@staticmethod
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def io(eem, eem_aux, iostandard):
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@ -19,6 +19,21 @@ def peripheral_dio(module, peripheral, **kwargs):
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edge_counter_cls=edge_counter_cls, **kwargs)
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def peripheral_dio_spi(module, peripheral, **kwargs):
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ttl_classes = {
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"input": ttl_serdes_7series.InOut_8X,
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"output": ttl_serdes_7series.Output_8X
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}
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if len(peripheral["ports"]) != 1:
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raise ValueError("peripheral dio_spi must be assigned one port")
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spi = [(s["clk"], s.get("mosi"), s.get("miso"), s.get("cs", []))
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for s in peripheral["spi"]]
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ttl = [(t["pin"], ttl_classes[t["direction"]],
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edge_counter.SimpleEdgeCounter if t.get("edge_counter") else None)
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for t in peripheral.get("ttl", [])]
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eem.DIO_SPI.add_std(module, peripheral["ports"][0], spi, ttl, **kwargs)
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def peripheral_urukul(module, peripheral, **kwargs):
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if len(peripheral["ports"]) == 1:
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port, port_aux = peripheral["ports"][0], None
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@ -119,6 +134,7 @@ def peripheral_hvamp(module, peripheral, **kwargs):
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peripheral_processors = {
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"dio": peripheral_dio,
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"dio_spi": peripheral_dio_spi,
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"urukul": peripheral_urukul,
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"novogorny": peripheral_novogorny,
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"sampler": peripheral_sampler,
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