From c428800caf52a77a22a9be0d967715cccb4e0b63 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Thu, 27 Oct 2016 15:39:39 +0200 Subject: [PATCH] phaser: spi, sma_gpio: 2.5 V --- artiq/gateware/phaser.py | 6 +++--- artiq/gateware/targets/kc705.py | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/artiq/gateware/phaser.py b/artiq/gateware/phaser.py index 4673b7b90..ca6185764 100644 --- a/artiq/gateware/phaser.py +++ b/artiq/gateware/phaser.py @@ -13,10 +13,10 @@ fmc_adapter_io = [ Subsignal("mosi", Pins("HPC:LA03_N")), Subsignal("miso", Pins("HPC:LA04_P")), Subsignal("en", Pins("HPC:LA05_N")), - IOStandard("LVTTL"), + IOStandard("LVCMOS25"), ), - ("ad9154_txen", 0, Pins("HPC:LA07_P"), IOStandard("LVTTL")), - ("ad9154_txen", 1, Pins("HPC:LA07_N"), IOStandard("LVTTL")), + ("ad9154_txen", 0, Pins("HPC:LA07_P"), IOStandard("LVCMOS25")), + ("ad9154_txen", 1, Pins("HPC:LA07_N"), IOStandard("LVCMOS25")), ("ad9154_refclk", 0, Subsignal("p", Pins("HPC:GBTCLK0_M2C_P")), Subsignal("n", Pins("HPC:GBTCLK0_M2C_N")), diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index f3abcd3ec..d6b1fede2 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -537,7 +537,7 @@ class Phaser(_NIST_Ions): rtio_channels = [] phy = ttl_serdes_7series.Inout_8X( - platform.request("user_sma_gpio_n_33")) + platform.request("user_sma_gpio_n")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128))