mirror of https://github.com/m-labs/artiq.git
drtio: support for local RTIO core
This commit is contained in:
parent
d37b73fd31
commit
c419c422fa
|
@ -83,5 +83,66 @@
|
||||||
"arguments": {"channel": 9}
|
"arguments": {"channel": 9}
|
||||||
},
|
},
|
||||||
|
|
||||||
|
"led0": {
|
||||||
|
"type": "local",
|
||||||
|
"module": "artiq.coredevice.ttl",
|
||||||
|
"class": "TTLOut",
|
||||||
|
"arguments": {"channel": 0x010000},
|
||||||
|
},
|
||||||
|
"led1": {
|
||||||
|
"type": "local",
|
||||||
|
"module": "artiq.coredevice.ttl",
|
||||||
|
"class": "TTLOut",
|
||||||
|
"arguments": {"channel": 0x010001},
|
||||||
|
},
|
||||||
|
"led2": {
|
||||||
|
"type": "local",
|
||||||
|
"module": "artiq.coredevice.ttl",
|
||||||
|
"class": "TTLOut",
|
||||||
|
"arguments": {"channel": 0x010002},
|
||||||
|
},
|
||||||
|
"led3": {
|
||||||
|
"type": "local",
|
||||||
|
"module": "artiq.coredevice.ttl",
|
||||||
|
"class": "TTLOut",
|
||||||
|
"arguments": {"channel": 0x010003},
|
||||||
|
},
|
||||||
|
"led4": {
|
||||||
|
"type": "local",
|
||||||
|
"module": "artiq.coredevice.ttl",
|
||||||
|
"class": "TTLOut",
|
||||||
|
"arguments": {"channel": 0x010004},
|
||||||
|
},
|
||||||
|
"led5": {
|
||||||
|
"type": "local",
|
||||||
|
"module": "artiq.coredevice.ttl",
|
||||||
|
"class": "TTLOut",
|
||||||
|
"arguments": {"channel": 0x010005},
|
||||||
|
},
|
||||||
|
"led6": {
|
||||||
|
"type": "local",
|
||||||
|
"module": "artiq.coredevice.ttl",
|
||||||
|
"class": "TTLOut",
|
||||||
|
"arguments": {"channel": 0x010006},
|
||||||
|
},
|
||||||
|
"led7": {
|
||||||
|
"type": "local",
|
||||||
|
"module": "artiq.coredevice.ttl",
|
||||||
|
"class": "TTLOut",
|
||||||
|
"arguments": {"channel": 0x010007},
|
||||||
|
},
|
||||||
|
|
||||||
|
"smap": {
|
||||||
|
"type": "local",
|
||||||
|
"module": "artiq.coredevice.ttl",
|
||||||
|
"class": "TTLOut",
|
||||||
|
"arguments": {"channel": 0x010008}
|
||||||
|
},
|
||||||
|
"sman": {
|
||||||
|
"type": "local",
|
||||||
|
"module": "artiq.coredevice.ttl",
|
||||||
|
"class": "TTLOut",
|
||||||
|
"arguments": {"channel": 0x010009}
|
||||||
|
},
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -4,17 +4,24 @@ from artiq.experiment import *
|
||||||
class BlinkForever(EnvExperiment):
|
class BlinkForever(EnvExperiment):
|
||||||
def build(self):
|
def build(self):
|
||||||
self.setattr_device("core")
|
self.setattr_device("core")
|
||||||
self.leds = [self.get_device("rled" + str(i)) for i in range(8)]
|
self.rleds = [self.get_device("rled" + str(i)) for i in range(8)]
|
||||||
|
self.leds = [self.get_device("led" + str(i)) for i in range(8)]
|
||||||
|
|
||||||
@kernel
|
@kernel
|
||||||
def run(self):
|
def run(self):
|
||||||
self.core.reset()
|
self.core.reset()
|
||||||
|
|
||||||
while True:
|
while True:
|
||||||
for led in self.leds:
|
with parallel:
|
||||||
led.pulse(250*ms)
|
for led in self.leds:
|
||||||
|
led.pulse(250*ms)
|
||||||
|
for led in self.rleds:
|
||||||
|
led.pulse(250*ms)
|
||||||
t = now_mu()
|
t = now_mu()
|
||||||
for led in self.leds:
|
for led in self.leds:
|
||||||
at_mu(t)
|
at_mu(t)
|
||||||
led.pulse(500*ms)
|
led.pulse(500*ms)
|
||||||
|
for led in self.rleds:
|
||||||
|
at_mu(t)
|
||||||
|
led.pulse(500*ms)
|
||||||
delay(250*ms)
|
delay(250*ms)
|
||||||
|
|
|
@ -1,4 +1,4 @@
|
||||||
from artiq.gateware.rtio.cri import KernelInitiator
|
from artiq.gateware.rtio.cri import KernelInitiator, CRIDecoder
|
||||||
from artiq.gateware.rtio.core import Channel, LogChannel, Core
|
from artiq.gateware.rtio.core import Channel, LogChannel, Core
|
||||||
from artiq.gateware.rtio.analyzer import Analyzer
|
from artiq.gateware.rtio.analyzer import Analyzer
|
||||||
from artiq.gateware.rtio.moninj import MonInj
|
from artiq.gateware.rtio.moninj import MonInj
|
||||||
|
|
|
@ -116,3 +116,34 @@ class KernelInitiator(Module, AutoCSR):
|
||||||
self.o_data.we.eq(self.o_timestamp.re),
|
self.o_data.we.eq(self.o_timestamp.re),
|
||||||
]
|
]
|
||||||
self.sync += If(self.counter_update.re, self.counter.status.eq(self.cri.counter))
|
self.sync += If(self.counter_update.re, self.counter.status.eq(self.cri.counter))
|
||||||
|
|
||||||
|
|
||||||
|
class CRIDecoder(Module):
|
||||||
|
def __init__(self, slaves=2, master=None):
|
||||||
|
if isinstance(slaves, int):
|
||||||
|
slaves = [Interface() for _ in range(slaves)]
|
||||||
|
if master is None:
|
||||||
|
master = Interface()
|
||||||
|
self.slaves = slaves
|
||||||
|
self.master = master
|
||||||
|
|
||||||
|
# # #
|
||||||
|
|
||||||
|
selected = Signal(8)
|
||||||
|
self.sync += selected.eq(self.master.chan_sel[16:])
|
||||||
|
|
||||||
|
# master -> slave
|
||||||
|
for n, slave in enumerate(slaves):
|
||||||
|
for name, size, direction in _layout:
|
||||||
|
if direction == DIR_M_TO_S and name != "cmd":
|
||||||
|
self.comb += getattr(slave, name).eq(getattr(master, name))
|
||||||
|
self.comb += If(selected == n, slave.cmd.eq(master.cmd))
|
||||||
|
|
||||||
|
# slave -> master
|
||||||
|
cases = dict()
|
||||||
|
for n, slave in enumerate(slaves):
|
||||||
|
cases[n] = []
|
||||||
|
for name, size, direction in _layout:
|
||||||
|
if direction == DIR_S_TO_M:
|
||||||
|
cases[n].append(getattr(master, name).eq(getattr(slave, name)))
|
||||||
|
self.comb += Case(selected, cases)
|
||||||
|
|
|
@ -9,6 +9,7 @@ from misoc.integration.builder import builder_args, builder_argdict
|
||||||
|
|
||||||
from artiq.gateware.soc import AMPSoC, build_artiq_soc
|
from artiq.gateware.soc import AMPSoC, build_artiq_soc
|
||||||
from artiq.gateware import rtio
|
from artiq.gateware import rtio
|
||||||
|
from artiq.gateware.rtio.phy import ttl_simple
|
||||||
from artiq.gateware.drtio.transceiver import gtx_7series
|
from artiq.gateware.drtio.transceiver import gtx_7series
|
||||||
from artiq.gateware.drtio import DRTIOMaster
|
from artiq.gateware.drtio import DRTIOMaster
|
||||||
from artiq import __version__ as artiq_version
|
from artiq import __version__ as artiq_version
|
||||||
|
@ -42,10 +43,23 @@ class Master(MiniSoC, AMPSoC):
|
||||||
sys_clk_freq=self.clk_freq,
|
sys_clk_freq=self.clk_freq,
|
||||||
clock_div2=True)
|
clock_div2=True)
|
||||||
self.submodules.drtio = DRTIOMaster(self.transceiver)
|
self.submodules.drtio = DRTIOMaster(self.transceiver)
|
||||||
self.submodules.rtio = rtio.KernelInitiator(self.drtio.cri)
|
|
||||||
self.register_kernel_cpu_csrdevice("rtio")
|
|
||||||
self.csr_devices.append("drtio")
|
self.csr_devices.append("drtio")
|
||||||
|
|
||||||
|
rtio_channels = []
|
||||||
|
for i in range(8):
|
||||||
|
phy = ttl_simple.Output(platform.request("user_led", i))
|
||||||
|
self.submodules += phy
|
||||||
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||||
|
for sma in "user_sma_gpio_p", "user_sma_gpio_n":
|
||||||
|
phy = ttl_simple.Inout(platform.request(sma))
|
||||||
|
self.submodules += phy
|
||||||
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||||
|
self.submodules.rtio_core = rtio.Core(rtio_channels)
|
||||||
|
|
||||||
|
self.submodules.cridec = rtio.CRIDecoder([self.drtio.cri, self.rtio_core.cri])
|
||||||
|
self.submodules.rtio = rtio.KernelInitiator(self.cridec.cri)
|
||||||
|
self.register_kernel_cpu_csrdevice("rtio")
|
||||||
|
|
||||||
|
|
||||||
def main():
|
def main():
|
||||||
parser = argparse.ArgumentParser(
|
parser = argparse.ArgumentParser(
|
||||||
|
|
Loading…
Reference in New Issue