From c39987b61792082c72e62d08d5e77322b4c9e03a Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 24 Oct 2016 20:46:55 +0800 Subject: [PATCH] drtio: handle underflow/sequence error CSRs --- artiq/gateware/drtio/rt_controller.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/artiq/gateware/drtio/rt_controller.py b/artiq/gateware/drtio/rt_controller.py index a8c313fc0..69eb09b6f 100644 --- a/artiq/gateware/drtio/rt_controller.py +++ b/artiq/gateware/drtio/rt_controller.py @@ -81,6 +81,14 @@ class RTController(Module): status_sequence_error = Signal() self.comb += self.kcsrs.o_status.status.eq(Cat( status_wait, status_underflow, status_sequence_error)) + sequence_error_set = Signal() + underflow_set = Signal() + self.sync += [ + If(self.kcsrs.o_underflow_reset.re, status_underflow.eq(0)), + If(self.kcsrs.o_sequence_error_reset, status_sequence_error.eq(0)), + If(underflow_set, status_underflow.eq(1)), + If(sequence_error_set, status_sequence_error.eq(1)), + ] # TODO: collision, replace, busy cond_sequence_error = self.o_timestamp.storage < last_timestamps.dat_r