mirror of https://github.com/m-labs/artiq.git
master: only local rtio events in analyzer
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@ -577,7 +577,7 @@ class SatelliteBase(BaseSoC):
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
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self.csr_devices.append("routing_table")
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self.csr_devices.append("routing_table")
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.cri_con.switch.slave,
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.rtio_core.cri,
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self.get_native_sdram_if(), cpu_dw=self.cpu_dw)
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self.get_native_sdram_if(), cpu_dw=self.cpu_dw)
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self.csr_devices.append("rtio_analyzer")
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self.csr_devices.append("rtio_analyzer")
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