From c2667debf82b457a3532414a9ebfe0e6db31fe49 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 6 Apr 2017 16:33:59 +0800 Subject: [PATCH] drtio: test replace in RTL simulation --- artiq/gateware/test/drtio/test_full_stack.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/test/drtio/test_full_stack.py b/artiq/gateware/test/drtio/test_full_stack.py index 66bbd4982..59e5b2897 100644 --- a/artiq/gateware/test/drtio/test_full_stack.py +++ b/artiq/gateware/test/drtio/test_full_stack.py @@ -143,7 +143,8 @@ class TestFullStack(unittest.TestCase): delay(200*8) yield from write(0, 1) delay(5*8) - yield from write(0, 0) + yield from write(0, 1) + yield from write(0, 0) # replace yield from write(1, 1) delay(6*8) yield from write(1, 0) @@ -159,7 +160,7 @@ class TestFullStack(unittest.TestCase): self.assertNotEqual((yield dut.phy2.received_data), correct_large_data) delay(10*8) yield from write(2, correct_large_data) - for i in range(40): + for i in range(45): yield self.assertEqual((yield dut.phy2.received_data), correct_large_data)