M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 19:28:26 +08:00
Code Issues Projects Releases Wiki Activity

coredevice/spi: read_sync read bit

Browse Source
This commit is contained in:
Robert Jördens 2016-02-29 14:55:29 +01:00
parent df7d15d1fe
commit c226aeb0d4
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
artiq/coredevice/spi.py
View File

@ -15,6 +15,8 @@ SPI_DATA_ADDR, SPI_XFER_ADDR, SPI_CONFIG_ADDR = range(3)
SPI_HALF_DUPLEX,
) = (1 << i for i in range(8))
SPI_RT2WB_READ = 1 << 2
class SPIMaster:
"""Core device Serial Peripheral Interface (SPI) bus master.
@ -73,7 +75,7 @@ class SPIMaster:
@kernel
def read_sync(self):
r = rt2wb_read_sync(now_mu(), self.channel, SPI_DATA_ADDR,
int(self.ref_period_mu))
r = rt2wb_read_sync(now_mu(), self.channel, SPI_DATA_ADDR |
SPI_RT2WB_READ, int(self.ref_period_mu))
delay_mu(self.ref_period_mu)
return r