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coredevice/spi: read_sync read bit

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This commit is contained in:
Robert Jördens 2016-02-29 14:55:29 +01:00
parent df7d15d1fe
commit c226aeb0d4
1 changed files with 4 additions and 2 deletions
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6
artiq/coredevice/spi.py
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@ -15,6 +15,8 @@ SPI_DATA_ADDR, SPI_XFER_ADDR, SPI_CONFIG_ADDR = range(3)
SPI_HALF_DUPLEX, SPI_HALF_DUPLEX,
) = (1 << i for i in range(8)) ) = (1 << i for i in range(8))
SPI_RT2WB_READ = 1 << 2
class SPIMaster: class SPIMaster:
"""Core device Serial Peripheral Interface (SPI) bus master. """Core device Serial Peripheral Interface (SPI) bus master.
@ -73,7 +75,7 @@ class SPIMaster:
@kernel @kernel
def read_sync(self): def read_sync(self):
r = rt2wb_read_sync(now_mu(), self.channel, SPI_DATA_ADDR, r = rt2wb_read_sync(now_mu(), self.channel, SPI_DATA_ADDR |
int(self.ref_period_mu)) SPI_RT2WB_READ, int(self.ref_period_mu))
delay_mu(self.ref_period_mu) delay_mu(self.ref_period_mu)
return r return r