From c0ca27e6cff582fb5a7fba5b35d4b4f100f55f24 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Wed, 10 May 2023 10:27:41 +0800 Subject: [PATCH] satellite: add rtio_analyzer, only for local rtio --- artiq/gateware/targets/kasli.py | 6 +++++- artiq/gateware/targets/kc705.py | 7 +++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index ecb49451f..4322972aa 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -360,7 +360,7 @@ class MasterBase(MiniSoC, AMPSoC): self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) self.csr_devices.append("routing_table") - self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.cri_con.switch.slave, + self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.rtio_core.cri, self.get_native_sdram_if(), cpu_dw=self.cpu_dw) self.csr_devices.append("rtio_analyzer") @@ -576,6 +576,10 @@ class SatelliteBase(BaseSoC): self.csr_devices.append("cri_con") self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) self.csr_devices.append("routing_table") + + self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.cri_con.switch.slave, + self.get_native_sdram_if(), cpu_dw=self.cpu_dw) + self.csr_devices.append("rtio_analyzer") class Master(MasterBase): diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 6444410cd..70733dfe3 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -308,6 +308,10 @@ class _MasterBase(MiniSoC, AMPSoC): self.register_kernel_cpu_csrdevice("cri_con") self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) self.csr_devices.append("routing_table") + self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.rtio_core.cri, + self.get_native_sdram_if(), cpu_dw=self.cpu_dw) + self.csr_devices.append("rtio_analyzer") + class _SatelliteBase(BaseSoC): @@ -460,6 +464,9 @@ class _SatelliteBase(BaseSoC): self.csr_devices.append("cri_con") self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) self.csr_devices.append("routing_table") + self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.rtio_core.cri, + self.get_native_sdram_if(), cpu_dw=self.cpu_dw) + self.csr_devices.append("rtio_analyzer") class _NIST_CLOCK_RTIO: