mirror of https://github.com/m-labs/artiq.git
rtio: fix indentation
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@ -90,8 +90,8 @@ class _OutputManager(Module):
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# Note: replace may be asserted at the same time as collision
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# Note: replace may be asserted at the same time as collision
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# when addresses are different. In that case, it is a collision.
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# when addresses are different. In that case, it is a collision.
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self.sync.rsys += replace.eq(self.ev.timestamp == buf.timestamp)
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self.sync.rsys += replace.eq(self.ev.timestamp == buf.timestamp)
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# Detect sequence errors on coarse timestamps only
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# Detect sequence errors on coarse timestamps only
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# so that they are mutually exclusive with collision errors.
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# so that they are mutually exclusive with collision errors.
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self.sync.rsys += sequence_error.eq(self.ev.timestamp[fine_ts_width:] <
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self.sync.rsys += sequence_error.eq(self.ev.timestamp[fine_ts_width:] <
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buf.timestamp[fine_ts_width:])
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buf.timestamp[fine_ts_width:])
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if interface.enable_replace:
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if interface.enable_replace:
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