mirror of https://github.com/m-labs/artiq.git
compiler/targets: Fix refactoring leftover for native (host) target
It's unclear whether this actually caused any issues, or why this wasn't done before (instead just setting the now-removed endianness flag).
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@ -263,7 +263,7 @@ class NativeTarget(Target):
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def __init__(self):
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def __init__(self):
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super().__init__()
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super().__init__()
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self.triple = llvm.get_default_triple()
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self.triple = llvm.get_default_triple()
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host_data_layout = str(llvm.targets.Target.from_default_triple().create_target_machine().target_data)
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self.data_layout = str(llvm.targets.Target.from_default_triple().create_target_machine().target_data)
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class RV32IMATarget(Target):
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class RV32IMATarget(Target):
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triple = "riscv32-unknown-linux"
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triple = "riscv32-unknown-linux"
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