mirror of https://github.com/m-labs/artiq.git
targets/artiq_kc705: add false path between rsys_clk and rio_clk (reduce P&R on AMP from 40 minutes to 5 minutes :)
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@ -2,6 +2,7 @@ from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.bank.description import *
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from migen.bank import wbgen
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from migen.bank import wbgen
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from mibuild.generic_platform import *
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from mibuild.generic_platform import *
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from mibuild.xilinx.vivado import XilinxVivadoToolchain
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from misoclib.com import gpio
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from misoclib.com import gpio
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from misoclib.soc import mem_decoder
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from misoclib.soc import mem_decoder
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@ -72,6 +73,13 @@ class _Peripherals(MiniSoC):
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self.submodules.dds = ad9858.AD9858(dds_pads)
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self.submodules.dds = ad9858.AD9858(dds_pads)
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self.comb += dds_pads.fud_n.eq(~fud)
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self.comb += dds_pads.fud_n.eq(~fud)
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if isinstance(platform.toolchain, XilinxVivadoToolchain):
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platform.add_platform_command("""
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create_clock -name rsys_clk -period 8.0 [get_nets rsys_clk]
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create_clock -name rio_clk -period 8.0 [get_nets rio_clk]
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set_false_path -from [get_clocks rsys_clk] -to [get_clocks rio_clk]
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set_false_path -from [get_clocks rio_clk] -to [get_clocks rsys_clk]
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""")
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class UP(_Peripherals):
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class UP(_Peripherals):
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def __init__(self, *args, **kwargs):
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def __init__(self, *args, **kwargs):
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