From bd968211de27b556448e420dfa8ada76edc3914f Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 6 Aug 2018 00:27:10 +0800 Subject: [PATCH] ad9154: use continuous sync mode --- artiq/firmware/libboard_artiq/ad9154.rs | 29 +++++--------------- artiq/firmware/libboard_artiq/jesd204sync.rs | 22 +++++++-------- 2 files changed, 18 insertions(+), 33 deletions(-) diff --git a/artiq/firmware/libboard_artiq/ad9154.rs b/artiq/firmware/libboard_artiq/ad9154.rs index 978f2a199..87aa8e29f 100644 --- a/artiq/firmware/libboard_artiq/ad9154.rs +++ b/artiq/firmware/libboard_artiq/ad9154.rs @@ -371,27 +371,9 @@ fn dac_setup(dacno: u8, linerate: u64) -> Result<(), &'static str> { write(ad9154_reg::LMFC_VAR_1, 0x0a); write(ad9154_reg::SYNC_ERRWINDOW, 0); // +- 1/2 DAC clock write(ad9154_reg::SYNC_CONTROL, - 0x9*ad9154_reg::SYNCMODE | 0*ad9154_reg::SYNCENABLE | - 0*ad9154_reg::SYNCARM | 1*ad9154_reg::SYNCCLRSTKY | + 0x2*ad9154_reg::SYNCMODE | 1*ad9154_reg::SYNCENABLE | 1*ad9154_reg::SYNCCLRLAST); - write(ad9154_reg::SYNC_CONTROL, - 0x9*ad9154_reg::SYNCMODE | 1*ad9154_reg::SYNCENABLE | - 0*ad9154_reg::SYNCARM | 1*ad9154_reg::SYNCCLRSTKY | - 1*ad9154_reg::SYNCCLRLAST); - write(ad9154_reg::SYNC_CONTROL, - 0x9*ad9154_reg::SYNCMODE | 1*ad9154_reg::SYNCENABLE | - 1*ad9154_reg::SYNCARM | 0*ad9154_reg::SYNCCLRSTKY | - 0*ad9154_reg::SYNCCLRLAST); - clock::spin_us(1000); // ensure at least one sysref edge - if read(ad9154_reg::SYNC_CONTROL) & ad9154_reg::SYNCARM != 0 { - return Err("no sysref edge"); - } - if read(ad9154_reg::SYNC_STATUS) & ad9154_reg::SYNC_LOCK == 0 { - return Err("no sync lock"); - } - if read(ad9154_reg::SYNC_STATUS) & ad9154_reg::SYNC_WLIM != 0 { - return Err("sysref phase error"); - } + write(ad9154_reg::XBAR_LN_0_1, 0*ad9154_reg::LOGICAL_LANE0_SRC | 1*ad9154_reg::LOGICAL_LANE1_SRC); write(ad9154_reg::XBAR_LN_2_3, @@ -689,9 +671,12 @@ fn dac_cfg_retry(dacno: u8) -> Result<(), &'static str> { pub fn dac_get_sync_error(dacno: u8) -> u16 { spi_setup(dacno); - let sync_error = ((read(ad9154_reg::SYNC_CURRERR_L) as u16) | - ((read(ad9154_reg::SYNC_CURRERR_H) as u16) << 8)) + let sync_error = ((read(ad9154_reg::SYNC_LASTERR_L) as u16) | + ((read(ad9154_reg::SYNC_LASTERR_H) as u16) << 8)) & 0x1ff; + write(ad9154_reg::SYNC_CONTROL, + 0x2*ad9154_reg::SYNCMODE | 1*ad9154_reg::SYNCENABLE | + 1*ad9154_reg::SYNCCLRLAST); sync_error } diff --git a/artiq/firmware/libboard_artiq/jesd204sync.rs b/artiq/firmware/libboard_artiq/jesd204sync.rs index 81cf72cac..4510de794 100644 --- a/artiq/firmware/libboard_artiq/jesd204sync.rs +++ b/artiq/firmware/libboard_artiq/jesd204sync.rs @@ -148,13 +148,13 @@ fn sysref_cal_dac(dacno: u8) -> Result { hmc7043::sysref_offset_dac(dacno, d); clock::spin_us(10000); - let sync_error_last = ad9154::dac_get_sync_error(dacno); + ad9154::dac_get_sync_error(dacno); // clear SYNC_LASTERR loop { hmc7043::sysref_offset_dac(dacno, d); clock::spin_us(10000); let sync_error = ad9154::dac_get_sync_error(dacno); - if sync_error != sync_error_last { + if sync_error != 0 { dmin = d; break; } @@ -165,16 +165,16 @@ fn sysref_cal_dac(dacno: u8) -> Result { } } - d += 5; // get away from jitter + d += 17; // get away from jitter hmc7043::sysref_offset_dac(dacno, d); clock::spin_us(10000); - let sync_error_last = ad9154::dac_get_sync_error(dacno); + ad9154::dac_get_sync_error(dacno); // clear SYNC_LASTERR loop { hmc7043::sysref_offset_dac(dacno, d); clock::spin_us(10000); let sync_error = ad9154::dac_get_sync_error(dacno); - if sync_error != sync_error_last { + if sync_error != 0 { dmax = d; break; } @@ -198,13 +198,13 @@ fn sysref_dac_align(dacno: u8, phase: u16) -> Result<(), &'static str> { hmc7043::sysref_offset_dac(dacno, phase); clock::spin_us(10000); - let sync_error_last = ad9154::dac_get_sync_error(dacno); + ad9154::dac_get_sync_error(dacno); // clear SYNC_LASTERR for d in 0..128 { hmc7043::sysref_offset_dac(dacno, phase - d); clock::spin_us(10000); let sync_error = ad9154::dac_get_sync_error(dacno); - if sync_error != sync_error_last { - info!(" sync error-: {} -> {}", sync_error_last, sync_error); + if sync_error != 0 { + info!(" sync error-: {}", sync_error); margin_minus = Some(d); break; } @@ -212,13 +212,13 @@ fn sysref_dac_align(dacno: u8, phase: u16) -> Result<(), &'static str> { hmc7043::sysref_offset_dac(dacno, phase); clock::spin_us(10000); - let sync_error_last = ad9154::dac_get_sync_error(dacno); + ad9154::dac_get_sync_error(dacno); // clear SYNC_LASTERR for d in 0..128 { hmc7043::sysref_offset_dac(dacno, phase + d); clock::spin_us(10000); let sync_error = ad9154::dac_get_sync_error(dacno); - if sync_error != sync_error_last { - info!(" sync error+: {} -> {}", sync_error_last, sync_error); + if sync_error != 0 { + info!(" sync error+: {}", sync_error); margin_plus = Some(d); break; }