mirror of https://github.com/m-labs/artiq.git
libboard/ad9154: update for sayma (spi, jesd parameters, linerate), breaks kc705/ad9154 fmc support
This commit is contained in:
Florent Kermarrec
parent
8b8da39a8f
commit
bd75954192
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@ -5,7 +5,7 @@ use ad9154_reg;
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fn spi_setup(dacno: u8) {
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unsafe {
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csr::converter_spi::offline_write(1);
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csr::converter_spi::cs_polarity_write(0);
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csr::converter_spi::cs_polarity_write(0b0001);
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csr::converter_spi::clk_polarity_write(0);
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csr::converter_spi::clk_phase_write(0);
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csr::converter_spi::lsb_first_write(0);
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@ -71,11 +71,10 @@ fn jesd_jsync(dacno: u8) -> bool {
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}
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}
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// ad9154 mode 2
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// external clk=300MHz
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// pclock=150MHz
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// ad9154 mode 1
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// linerate 6Gbps
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// deviceclock_fpga=150MHz
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// deviceclock_dac=300MHz
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// deviceclock_dac=600MHz
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struct JESDSettings {
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did: u8,
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@ -120,20 +119,20 @@ const JESD_SETTINGS: JESDSettings = JESDSettings {
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did: 0x5a,
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bid: 0x5,
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l: 4,
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l: 8,
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m: 4,
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n: 16,
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np: 16,
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f: 2,
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s: 1,
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s: 2,
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k: 16,
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cs: 1,
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cs: 0,
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subclassv: 1,
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jesdv: 1
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};
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fn dac_setup() -> Result<(), &'static str> {
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fn dac_setup(linerate: u64) -> Result<(), &'static str> {
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// reset
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write(ad9154_reg::SPI_INTFCONFA,
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1*ad9154_reg::SOFTRESET_M | 1*ad9154_reg::SOFTRESET |
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@ -148,9 +147,12 @@ fn dac_setup() -> Result<(), &'static str> {
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1*ad9154_reg::SDOACTIVE_M | 1*ad9154_reg::SDOACTIVE);
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clock::spin_us(100);
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if (read(ad9154_reg::PRODIDH) as u16) << 8 | (read(ad9154_reg::PRODIDL) as u16) != 0x9154 {
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return Err("AD9154 not found")
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return Err("AD9154 not found");
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} else {
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info!("AD9154 found");
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}
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info!("AD9154 configuration...");
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write(ad9154_reg::PWRCNTRL0,
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0*ad9154_reg::PD_DAC0 | 0*ad9154_reg::PD_DAC1 |
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0*ad9154_reg::PD_DAC2 | 0*ad9154_reg::PD_DAC3 |
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@ -205,7 +207,7 @@ fn dac_setup() -> Result<(), &'static str> {
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write(ad9154_reg::PDP_AVG_TIME, 0*ad9154_reg::PDP_ENABLE);
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write(ad9154_reg::MASTER_PD, 0);
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write(ad9154_reg::PHY_PD, 0x0f); // power down lanes 0-3
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write(ad9154_reg::PHY_PD, 0x00); // lanes 0-7 enabled
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write(ad9154_reg::GENERIC_PD,
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0*ad9154_reg::PD_SYNCOUT0B |
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1*ad9154_reg::PD_SYNCOUT1B);
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@ -233,7 +235,7 @@ fn dac_setup() -> Result<(), &'static str> {
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write(ad9154_reg::ILS_HD_CF,
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0*ad9154_reg::HD | 0*ad9154_reg::CF);
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write(ad9154_reg::ILS_CHECKSUM, jesd_checksum(&JESD_SETTINGS));
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write(ad9154_reg::LANEDESKEW, 0x0f);
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write(ad9154_reg::LANEDESKEW, 0xff);
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for i in 0..8 {
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write(ad9154_reg::BADDISPARITY, 0*ad9154_reg::RST_IRQ_DIS |
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0*ad9154_reg::DISABLE_ERR_CNTR_DIS |
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@ -258,20 +260,33 @@ fn dac_setup() -> Result<(), &'static str> {
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write(ad9154_reg::CTRLREG2, 0*ad9154_reg::ILAS_MODE |
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0*ad9154_reg::THRESHOLD_MASK_EN);
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write(ad9154_reg::KVAL, 1); // *4*K multiframes during ILAS
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write(ad9154_reg::LANEENABLE, 0x0f); // CGS _after_ this
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write(ad9154_reg::LANEENABLE, 0xff); // CGS _after_ this
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write(ad9154_reg::TERM_BLK1_CTRLREG0, 1);
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write(ad9154_reg::TERM_BLK2_CTRLREG0, 1);
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write(ad9154_reg::SERDES_SPI_REG, 1);
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if linerate > 5_650_000_000 {
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write(ad9154_reg::CDR_OPERATING_MODE_REG_0,
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0*ad9154_reg::CDR_OVERSAMP | 0x2*ad9154_reg::CDR_RESERVED |
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1*ad9154_reg::ENHALFRATE);
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} else {
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write(ad9154_reg::CDR_OPERATING_MODE_REG_0,
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0*ad9154_reg::CDR_OVERSAMP | 0x2*ad9154_reg::CDR_RESERVED |
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0*ad9154_reg::ENHALFRATE);
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}
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write(ad9154_reg::CDR_RESET, 0);
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write(ad9154_reg::CDR_RESET, 1);
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if linerate > 5_650_000_000 {
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write(ad9154_reg::REF_CLK_DIVIDER_LDO,
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0x0*ad9154_reg::SPI_CDR_OVERSAMP |
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0*ad9154_reg::SPI_CDR_OVERSAMP |
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1*ad9154_reg::SPI_LDO_BYPASS_FILT |
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0*ad9154_reg::SPI_LDO_REF_SEL);
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} else {
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write(ad9154_reg::REF_CLK_DIVIDER_LDO,
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1*ad9154_reg::SPI_CDR_OVERSAMP |
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1*ad9154_reg::SPI_LDO_BYPASS_FILT |
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0*ad9154_reg::SPI_LDO_REF_SEL);
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}
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write(ad9154_reg::LDO_FILTER_1, 0x62); // magic
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write(ad9154_reg::LDO_FILTER_2, 0xc9); // magic
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write(ad9154_reg::LDO_FILTER_3, 0x0e); // magic
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@ -334,7 +349,7 @@ fn dac_setup() -> Result<(), &'static str> {
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let t = clock::get_ms();
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while read(ad9154_reg::PLL_STATUS) & ad9154_reg::SERDES_PLL_LOCK_RB == 0 {
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if clock::get_ms() > t + 200 {
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return Err("SERDES PLL lock timeout");
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return Err("AD9154 SERDES PLL lock timeout");
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}
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}
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@ -361,16 +376,16 @@ fn dac_setup() -> Result<(), &'static str> {
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0*ad9154_reg::SYNCCLRLAST);
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clock::spin_us(1000); // ensure at least one sysref edge
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if read(ad9154_reg::SYNC_STATUS) & ad9154_reg::SYNC_LOCK == 0 {
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return Err("no sync lock")
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return Err("A9154 no sync lock");
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}
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write(ad9154_reg::XBAR_LN_0_1,
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7*ad9154_reg::LOGICAL_LANE0_SRC | 6*ad9154_reg::LOGICAL_LANE1_SRC);
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0*ad9154_reg::LOGICAL_LANE0_SRC | 1*ad9154_reg::LOGICAL_LANE1_SRC);
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write(ad9154_reg::XBAR_LN_2_3,
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5*ad9154_reg::LOGICAL_LANE2_SRC | 4*ad9154_reg::LOGICAL_LANE3_SRC);
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2*ad9154_reg::LOGICAL_LANE2_SRC | 3*ad9154_reg::LOGICAL_LANE3_SRC);
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write(ad9154_reg::XBAR_LN_4_5,
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0*ad9154_reg::LOGICAL_LANE4_SRC | 0*ad9154_reg::LOGICAL_LANE5_SRC);
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4*ad9154_reg::LOGICAL_LANE4_SRC | 5*ad9154_reg::LOGICAL_LANE5_SRC);
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write(ad9154_reg::XBAR_LN_6_7,
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0*ad9154_reg::LOGICAL_LANE6_SRC | 0*ad9154_reg::LOGICAL_LANE7_SRC);
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6*ad9154_reg::LOGICAL_LANE6_SRC | 7*ad9154_reg::LOGICAL_LANE7_SRC);
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write(ad9154_reg::JESD_BIT_INVERSE_CTRL, 0x00);
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write(ad9154_reg::GENERAL_JRX_CTRL_0,
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0x1*ad9154_reg::LINK_EN | 0*ad9154_reg::LINK_PAGE |
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@ -378,7 +393,7 @@ fn dac_setup() -> Result<(), &'static str> {
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Ok(())
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}
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fn monitor() {
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fn dac_monitor() {
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write(ad9154_reg::IRQ_STATUS0, 0x00);
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write(ad9154_reg::IRQ_STATUS1, 0x00);
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write(ad9154_reg::IRQ_STATUS2, 0x00);
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@ -421,22 +436,19 @@ fn monitor() {
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write(ad9154_reg::IRQ_STATUS3, 0x00);
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}
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fn cfg(dacno: u8) -> Result<(), &'static str> {
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fn dac_cfg(dacno: u8) -> Result<(), &'static str> {
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spi_setup(dacno);
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// Release the JESD clock domain reset late, as we need to
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// set up clock chips before.
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jesd_unreset();
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jesd_enable(dacno, false);
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jesd_prbs(dacno, false);
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jesd_stpl(dacno, false);
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clock::spin_us(10000);
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jesd_enable(dacno, true);
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dac_setup()?;
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dac_setup(6_000_000_000)?;
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jesd_enable(dacno, false);
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clock::spin_us(10000);
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jesd_enable(dacno, true);
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monitor();
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dac_monitor();
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clock::spin_us(50000);
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let t = clock::get_ms();
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while !jesd_ready(dacno) {
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if clock::get_ms() > t + 200 {
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@ -444,29 +456,33 @@ fn cfg(dacno: u8) -> Result<(), &'static str> {
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}
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}
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clock::spin_us(10000);
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if read(ad9154_reg::CODEGRPSYNCFLG) != 0x0f {
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if read(ad9154_reg::CODEGRPSYNCFLG) != 0xff {
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return Err("bad CODEGRPSYNCFLG")
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}
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if !jesd_jsync(dacno) {
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return Err("bad SYNC")
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}
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if read(ad9154_reg::FRAMESYNCFLG) != 0x0f {
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if read(ad9154_reg::FRAMESYNCFLG) != 0xff {
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return Err("bad FRAMESYNCFLG")
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}
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if read(ad9154_reg::GOODCHKSUMFLG) != 0x0f {
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if read(ad9154_reg::GOODCHKSUMFLG) != 0xff {
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return Err("bad GOODCHECKSUMFLG")
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}
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if read(ad9154_reg::INITLANESYNCFLG) != 0x0f {
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if read(ad9154_reg::INITLANESYNCFLG) != 0xff {
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return Err("bad INITLANESYNCFLG")
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}
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Ok(())
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}
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pub fn init() -> Result<(), &'static str> {
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// Release the JESD clock domain reset late, as we need to
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// set up clock chips before.
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jesd_unreset();
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//for dacno in 0..csr::AD9154.len() {
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for dacno in 0..csr::AD9154.len() {
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let dacno = dacno as u8;
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debug!("setting up DAC #{}", dacno);
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cfg(dacno)?;
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debug!("setting up A9154-{} DAC...", dacno);
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dac_cfg(dacno)?;
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}
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Ok(())
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}
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