From bd3bcbce64b28ef9f1956bf158b7744fb0675aea Mon Sep 17 00:00:00 2001
From: Simon Renblad <srenblad@m-labs.hk>
Date: Tue, 16 Jul 2024 13:12:29 +0800
Subject: [PATCH] fastino: monitor probe dacs

---
 artiq/gateware/rtio/phy/fastino.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/artiq/gateware/rtio/phy/fastino.py b/artiq/gateware/rtio/phy/fastino.py
index 9fcc71390..5e94fa4f1 100644
--- a/artiq/gateware/rtio/phy/fastino.py
+++ b/artiq/gateware/rtio/phy/fastino.py
@@ -27,6 +27,7 @@ class Fastino(Module):
 
         # dac data words
         dacs = [Signal(16) for i in range(32)]
+        self.probes = dacs
 
         header = Record([
             ("cfg", 4),