M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq
2
0
Fork 1
Code Issues Projects Releases Wiki Activity

Configure HMC7043 to give deterministic phase differences between its outputs

pull/1054/head
Thomas Harty 2018-06-05 12:00:58 +01:00 committed by Sébastien Bourdeauducq
parent ac5c4913ec
commit bd1ac7cf3b
1 changed files with 10 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
artiq/firmware/libboard_artiq/hmc830_7043.rs
View File

@ -146,6 +146,7 @@ pub mod hmc7043 {
const DAC_CLK_DIV: u32 = 2;
const FPGA_CLK_DIV: u32 = 8;
const SYSREF_DIV: u32 = 128;
const HMC_SYSREF_DIV: u32 = SYSREF_DIV*8; // Must be <= 4MHz
// enabled, divider, analog phase shift, digital phase shift
const OUTPUT_CONFIG: [(bool, u32, u8, u8); 14] = [
@ -243,7 +244,6 @@ pub mod hmc7043 {
spi_setup();
info!("loading configuration...");
write(0x3, 0x10); // Disable SYSREF timer
write(0xA, 0x06); // Disable the REFSYNCIN input
write(0xB, 0x07); // Enable the CLKIN input as LVPECL
write(0x50, 0x1f); // Disable GPO pin
@ -257,14 +257,17 @@ pub mod hmc7043 {
(1 << 4) |
(1 << 5));
write(0x5c, (HMC_SYSREF_DIV & 0xff) as u8); // Set SYSREF timer divider
write(0x5d, ((HMC_SYSREF_DIV & 0x0f) >> 8) as u8);
for channel in 0..14 {
let channel_base = 0xc8 + 0x0a*(channel as u16);
let (enabled, divider, aphase, dphase) = OUTPUT_CONFIG[channel];
if enabled {
// Only clock channels need to be high-performance
if (channel % 2) == 0 { write(channel_base, 0x91); }
else { write(channel_base, 0x11); }
if (channel % 2) == 0 { write(channel_base, 0xd1); }
else { write(channel_base, 0x51); }
}
else { write(channel_base, 0x10); }
write(channel_base + 0x1, (divider & 0x0ff) as u8);
@ -279,7 +282,11 @@ pub mod hmc7043 {
write(channel_base + 0x8, 0x08)
}
write(0x1, 0x4a); // Reset dividers and FSMs
write(0x1, 0x48);
write(0x1, 0xc8); // Synchronize dividers
write(0x1, 0x40); // Unmute, high-performace/low-noise mode
info!(" ...done");
Ok(())