mirror of https://github.com/m-labs/artiq.git
sawg: wrap limits init values
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@ -89,10 +89,12 @@ class Config(Module):
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self.limits = [[Signal((width, True)), Signal((width, True))]
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for i in range(2)]
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limit = 1 << width - 1
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self.limits[0][0].reset = -limit
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self.limits[0][1].reset = limit - 1
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self.limits[1][0].reset = int(-limit/cordic_gain)
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self.limits[1][1].reset = int((limit - 1)/cordic_gain)
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self.limits[0][0].reset = Constant(-limit, (width, True))
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self.limits[0][1].reset = Constant(limit - 1, (width, True))
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self.limits[1][0].reset = Constant(int(-limit/cordic_gain),
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(width, True))
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self.limits[1][1].reset = Constant(int((limit - 1)/cordic_gain),
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(width, True))
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# TODO make persistent, add read-out/notification/clear
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self.clipped = [Signal(2) for i in range(2)]
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self.i = Endpoint([("addr", bits_for(4 + 2*len(self.limits) - 1)),
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@ -139,7 +141,7 @@ class Channel(Module, SatAddMixin):
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coeff = halfgen4_cascade(parallelism, width=.4, order=8)
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hbf = [ParallelHBFUpsampler(coeff, width=width + 1) for i in range(2)]
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self.submodules.b = b = SplineParallelDUC(
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widths._replace(a=width + 1, f=widths.f - width), orders,
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widths._replace(a=len(hbf[0].o[0]), f=widths.f - width), orders,
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parallelism=parallelism)
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cfg = Config(width, b.gain)
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u = Spline(width=widths.a, order=orders.a)
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@ -178,6 +180,8 @@ class Channel(Module, SatAddMixin):
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b.ce.eq(cfg.ce),
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u.o.ack.eq(cfg.ce),
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Cat(b.clr, a1.clr, a2.clr).eq(cfg.clr),
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Cat(b.xi).eq(Cat(hbf[0].o)),
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Cat(b.yi).eq(Cat(hbf[1].o)),
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]
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self.sync += [
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hbf[0].i.eq(self.sat_add(a1.xo[0], a2.xo[0],
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@ -185,11 +189,6 @@ class Channel(Module, SatAddMixin):
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hbf[1].i.eq(self.sat_add(a1.yo[0], a2.yo[0],
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limits=cfg.limits[1], clipped=None)), # ignore Q clip data
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]
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for i in range(parallelism):
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self.comb += [
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b.xi[i].eq(hbf[0].o[i]),
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b.yi[i].eq(hbf[1].o[i]),
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]
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# wire up outputs and q_{i,o} exchange
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for o, x, y in zip(self.o, b.xo, self.y_in):
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self.sync += [
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