From bc3b55b1a83f824612ae78a843b2b0925c33e495 Mon Sep 17 00:00:00 2001 From: David Nadlinger Date: Tue, 29 Oct 2019 21:17:09 +0000 Subject: [PATCH] gateware/eem: Force IOB=TRUE on Urukul SYNC output Without this, the final register in the SYNC signal TTLClockGen isn't (always) placed in the I/O tile, leading to more jitter than necessary, and causing "double window" artefacts. See sinara-hw/Urukul#16 for more details. (Patch based on work by Weida Zhang, testing by various members of the community in Oxford and elsewhere.) --- artiq/gateware/eem.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/eem.py b/artiq/gateware/eem.py index fad54969f..8a8ad40b8 100644 --- a/artiq/gateware/eem.py +++ b/artiq/gateware/eem.py @@ -87,7 +87,7 @@ class Urukul(_EEM): ), ] ttls = [(6, eem, "io_update"), - (7, eem, "dds_reset_sync_in")] + (7, eem, "dds_reset_sync_in", Misc("IOB=TRUE"))] if eem_aux is not None: ttls += [(0, eem_aux, "sync_clk"), (1, eem_aux, "sync_in"), @@ -97,12 +97,12 @@ class Urukul(_EEM): (5, eem_aux, "sw1"), (6, eem_aux, "sw2"), (7, eem_aux, "sw3")] - for i, j, sig in ttls: + for i, j, sig, *extra_args in ttls: ios.append( ("urukul{}_{}".format(eem, sig), 0, Subsignal("p", Pins(_eem_pin(j, i, "p"))), Subsignal("n", Pins(_eem_pin(j, i, "n"))), - IOStandard(iostandard) + IOStandard(iostandard), *extra_args )) return ios