perform RTIO init on comms CPU side

artiq/gateware/drtio/rt_controller.py

@@ -17,6 +17,9 @@ class _CSRs(AutoCSR):
         self.set_time = CSR()
         self.underflow_margin = CSRStorage(16, reset=200)
 
+        self.reset = CSR()
+        self.reset_phy = CSR()
+
         self.o_get_fifo_space = CSR()
         self.o_dbg_fifo_space = CSRStatus(16)
         self.o_dbg_last_timestamp = CSRStatus(64)
@@ -57,11 +60,11 @@ class RTController(Module):
         # reset
         self.sync += [
             If(rt_packets.reset_ack, rt_packets.reset_stb.eq(0)),
-            If(self.cri.cmd == cri.commands["reset"],
+            If(self.csrs.reset.re,
                 rt_packets.reset_stb.eq(1),
                 rt_packets.reset_phy.eq(0)
             ),
-            If(self.cri.cmd == cri.commands["reset_phy"],
+            If(self.csrs.reset_phy.re,
                 rt_packets.reset_stb.eq(1),
                 rt_packets.reset_phy.eq(1)
             ),

artiq/gateware/rtio/analyzer.py

@@ -78,8 +78,7 @@ class MessageEncoder(Module, AutoCSR):
             exception.channel.eq(kcsrs.chan_sel.storage),
             exception.rtio_counter.eq(rtio_counter),
         ]
-        for ename in ("reset", "reset_phy",
+        for ename in ("o_underflow_reset", "o_sequence_error_reset",
-                      "o_underflow_reset", "o_sequence_error_reset",
                       "o_collision_reset", "i_overflow_reset"):
             self.comb += \
                 If(getattr(kcsrs, ename).re,

artiq/gateware/rtio/core.py

@@ -5,6 +5,7 @@ from migen import *
 from migen.genlib.record import Record
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.resetsync import AsyncResetSynchronizer
+from misoc.interconnect.csr import *
 
 from artiq.gateware.rtio import cri, rtlink
 from artiq.gateware.rtio.cdc import *
@@ -264,13 +265,15 @@ class LogChannel:
         self.overrides = []
 
 
-class Core(Module):
+class Core(Module, AutoCSR):
     def __init__(self, channels, fine_ts_width=None, guard_io_cycles=20):
         if fine_ts_width is None:
             fine_ts_width = max(rtlink.get_fine_ts_width(c.interface)
                                 for c in channels)
 
         self.cri = cri.Interface()
+        self.reset = CSR()
+        self.reset_phy = CSR()
         self.comb += self.cri.arb_gnt.eq(1)
 
         # Clocking/Reset
@@ -279,8 +282,8 @@ class Core(Module):
         cmd_reset = Signal(reset=1)
         cmd_reset_phy = Signal(reset=1)
         self.sync += [
-            cmd_reset.eq(self.cri.cmd == cri.commands["reset"]),
+            cmd_reset.eq(self.reset.re),
-            cmd_reset_phy.eq(self.cri.cmd == cri.commands["reset_phy"])
+            cmd_reset_phy.eq(self.reset_phy.re)
         ]
         cmd_reset.attr.add("no_retiming")
         cmd_reset_phy.attr.add("no_retiming")

artiq/gateware/rtio/cri.py

@@ -8,17 +8,15 @@ from misoc.interconnect.csr import *
 
 commands = {
     "nop": 0,
-    "reset": 1,
-    "reset_phy": 2,
 
-    "write": 3,
+    "write": 1,
-    "read": 4,
+    "read": 2,
 
-    "o_underflow_reset": 5,
+    "o_underflow_reset": 3,
-    "o_sequence_error_reset": 6,
+    "o_sequence_error_reset": 4,
-    "o_collision_reset": 7,
+    "o_collision_reset": 5,
-    "o_busy_reset": 8,
+    "o_busy_reset": 6,
-    "i_overflow_reset": 9
+    "i_overflow_reset": 7
 }
 
 
@@ -57,8 +55,6 @@ class KernelInitiator(Module, AutoCSR):
         self.arb_req = CSRStorage()
         self.arb_gnt = CSRStatus()
 
-        self.reset = CSR()
-        self.reset_phy = CSR()
         self.chan_sel = CSRStorage(24)
 
         self.o_data = CSRStorage(512, write_from_dev=True)
@@ -91,8 +87,6 @@ class KernelInitiator(Module, AutoCSR):
             self.arb_gnt.status.eq(self.cri.arb_gnt),
 
             self.cri.cmd.eq(commands["nop"]),
-            If(self.reset.re, self.cri.cmd.eq(commands["reset"])),
-            If(self.reset_phy.re, self.cri.cmd.eq(commands["reset_phy"])),
             If(self.o_we.re, self.cri.cmd.eq(commands["write"])),
             If(self.i_re.re, self.cri.cmd.eq(commands["read"])),
             If(self.o_underflow_reset.re, self.cri.cmd.eq(commands["o_underflow_reset"])),

artiq/gateware/targets/kc705.py

@@ -144,6 +144,7 @@ class _NIST_Ions(MiniSoC, AMPSoC):
         self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
         self.csr_devices.append("rtio_crg")
         self.submodules.rtio_core = rtio.Core(rtio_channels)
+        self.csr_devices.append("rtio_core")
         self.submodules.rtio = rtio.KernelInitiator()
         self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
         self.register_kernel_cpu_csrdevice("rtio")

artiq/gateware/targets/pipistrello.py

@@ -218,6 +218,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
 
         # RTIO logic
         self.submodules.rtio_core = rtio.Core(rtio_channels)
+        self.csr_devices.append("rtio_core")
         self.submodules.rtio = rtio.KernelInitiator(self.rtio_core.cri)
         self.register_kernel_cpu_csrdevice("rtio")
         self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)

artiq/protocols/analyzer.py

@@ -9,9 +9,9 @@ class MessageType(Enum):
 
 
 class ExceptionType(Enum):
-    reset = 0b000000
+    legacy_reset = 0b000000
     legacy_reset_falling = 0b000001
-    reset_phy = 0b000010
+    legacy_reset_phy = 0b000010
     legacy_reset_phy_falling = 0b000011
 
     o_underflow_reset = 0b010000

artiq/runtime.rs/libksupport/rtio.rs

@@ -1,6 +1,11 @@
+#[path = "../src/kernel_proto.rs"]
+mod kernel_proto;
+
 use board::csr;
 use core::ptr::{read_volatile, write_volatile};
 use ::ArtiqList;
+use ::send;
+use kernel_proto::*;
 
 const RTIO_O_STATUS_FULL:           u32 = 1;
 const RTIO_O_STATUS_UNDERFLOW:      u32 = 2;
@@ -11,9 +16,7 @@ const RTIO_I_STATUS_EMPTY:          u32 = 1;
 const RTIO_I_STATUS_OVERFLOW:       u32 = 2;
 
 pub extern fn init() {
-    unsafe {
+    send(&RTIOInitRequest);
-        csr::rtio::reset_write(1);
-    }
 }
 
 pub extern fn get_counter() -> i64 {

artiq/runtime.rs/src/kernel_proto.rs

@@ -30,6 +30,8 @@ pub enum Message<'a> {
     NowInitReply(u64),
     NowSave(u64),
 
+    RTIOInitRequest,
+
     RunFinished,
     RunException {
         exception: Exception<'a>,

artiq/runtime.rs/src/session.rs

@@ -4,6 +4,7 @@ use std::cell::RefCell;
 use std::io::{self, Read, Write, BufWriter};
 use std::btree_set::BTreeSet;
 use {config, rtio_crg, clock, mailbox, rpc_queue, kernel};
+use board::csr;  // TODO: centralize (D)RTIO management
 use logger::BufferLogger;
 use cache::Cache;
 use urc::Urc;
@@ -377,6 +378,14 @@ fn process_kern_message(waiter: Waiter,
                 kern_acknowledge()
             }
 
+            &kern::RTIOInitRequest => {
+                info!("resetting RTIO");
+                unsafe {
+                    csr::rtio_core::reset_write(1);
+                }
+                kern_acknowledge()
+            }
+
             &kern::WatchdogSetRequest { ms } => {
                 let id = try!(session.watchdog_set.set_ms(ms)
                                 .map_err(|()| io_error("out of watchdogs")));