mirror of https://github.com/m-labs/artiq.git
sayma/serwb: remove scrambling (does not seems to work on sayma for now...)
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@ -174,7 +174,7 @@ class Standalone(MiniSoC, AMPSoC):
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self.submodules.serwb_phy_amc = serwb_phy_amc
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self.submodules.serwb_phy_amc = serwb_phy_amc
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self.csr_devices.append("serwb_phy_amc")
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self.csr_devices.append("serwb_phy_amc")
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serwb_core = serwb.core.SERWBCore(serwb_phy_amc, int(self.clk_freq), mode="slave", with_scrambling=True)
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serwb_core = serwb.core.SERWBCore(serwb_phy_amc, int(self.clk_freq), mode="slave", with_scrambling=False)
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self.submodules += serwb_core
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self.submodules += serwb_core
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self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
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self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
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@ -161,7 +161,7 @@ class SaymaRTM(Module):
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self.comb += self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.refclk)
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self.comb += self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.refclk)
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csr_devices.append("serwb_phy_rtm")
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csr_devices.append("serwb_phy_rtm")
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serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master", with_scrambling=True)
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serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master", with_scrambling=False)
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self.submodules += serwb_core
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self.submodules += serwb_core
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# process CSR devices and connect them to serwb
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# process CSR devices and connect them to serwb
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