M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

suservo: docstring fixes, revert parametrization of r_rtt

This commit is contained in:
Robert Jördens 2018-06-04 07:27:17 +00:00
parent 07a1425e51
commit bb87976d4f
1 changed files with 12 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
artiq/gateware/eem.py
View File

@ -443,15 +443,16 @@ class SUServo(_EEM):
@classmethod @classmethod
def add_std(cls, target, eems_sampler, eems_urukul0, eems_urukul1, def add_std(cls, target, eems_sampler, eems_urukul0, eems_urukul1,
t_rtt=8, clk=1, shift=11, profile=5): t_rtt=4, clk=1, shift=11, profile=5):
""" Adds an 8-channel Sampler-Urukul servo to target. """Add a 8-channel Sampler-Urukul Servo
:param t_rtt: upper estimate for clock round-trip propagation time from :param t_rtt: upper estimate for clock round-trip propagation time from
sck at the FPGA to clkout at the FPGA, measured in RTIO coarse ``sck`` at the FPGA to ``clkout`` at the FPGA, measured in RTIO
cycles (default: 8). This is the sum of the round-trip cabling coarse cycles (default: 4). This is the sum of the round-trip
delay and the 8ns max propagation delay on Sampler. With all cabling delay and the 8 ns max propagation delay on Sampler (ADC
other parameters at their default values, increasing t_rtt beyond 8 and LVDS drivers). Increasing ``t_rtt`` increases servo latency.
increases the servo latency With all other parameters at their default values, ``t_rtt`` values
above 4 also increase the servo period (reduce servo bandwidth).
:param clk: DDS SPI clock cycle half-width in RTIO coarse cycles :param clk: DDS SPI clock cycle half-width in RTIO coarse cycles
(default: 1) (default: 1)
:param shift: fixed-point scaling factor for IIR coefficients :param shift: fixed-point scaling factor for IIR coefficients
@ -459,7 +460,6 @@ class SUServo(_EEM):
:param profile: log2 of the number of profiles for each DDS channel :param profile: log2 of the number of profiles for each DDS channel
(default: 5) (default: 5)
""" """
cls.add_extension( cls.add_extension(
target, *(eems_sampler + eems_urukul0 + eems_urukul1)) target, *(eems_sampler + eems_urukul0 + eems_urukul1))
eem_sampler = "sampler{}".format(eems_sampler[0]) eem_sampler = "sampler{}".format(eems_sampler[0])
@ -471,8 +471,9 @@ class SUServo(_EEM):
target.platform, eem_urukul0, eem_urukul1) target.platform, eem_urukul0, eem_urukul1)
# timings in units of RTIO coarse period # timings in units of RTIO coarse period
adc_p = servo.ADCParams(width=16, channels=8, lanes=4, t_cnvh=4, adc_p = servo.ADCParams(width=16, channels=8, lanes=4, t_cnvh=4,
# account for SCK pipeline latency # account for SCK DDR to CONV latency
t_conv=57 - 4, t_rtt=t_rtt) # difference (4 cycles measured)
t_conv=57 - 4, t_rtt=t_rtt + 4)
iir_p = servo.IIRWidths(state=25, coeff=18, adc=16, asf=14, word=16, iir_p = servo.IIRWidths(state=25, coeff=18, adc=16, asf=14, word=16,
accu=48, shift=shift, channel=3, accu=48, shift=shift, channel=3,
profile=profile) profile=profile)