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artiq
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This commit is contained in:
Sebastien Bourdeauducq 2017-08-31 12:52:09 +08:00
parent 5a041c24f3
commit bacf8a1614
2 changed files with 2 additions and 2 deletions
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2
artiq/gateware/targets/kc705_drtio_master.py
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@ -59,7 +59,7 @@ class Master(MiniSoC, AMPSoC):
self.add_wb_slave(self.mem_map["drtio_aux"], 0x800, self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
self.drtio0.aux_controller.bus) self.drtio0.aux_controller.bus)
self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800) self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
self.config["has_drtio"] = None self.config["HAS_DRTIO"] = None
self.add_csr_group("drtio", ["drtio0"]) self.add_csr_group("drtio", ["drtio0"])
self.add_memory_group("drtio_aux", ["drtio0_aux"]) self.add_memory_group("drtio_aux", ["drtio0_aux"])

2
artiq/gateware/targets/kc705_drtio_satellite.py
View File

@ -64,7 +64,7 @@ class Satellite(BaseSoC):
self.add_wb_slave(self.mem_map["drtio_aux"], 0x800, self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
self.drtio0.aux_controller.bus) self.drtio0.aux_controller.bus)
self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800) self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
self.config["has_drtio"] = None self.config["HAS_DRTIO"] = None
self.add_csr_group("drtio", ["drtio0"]) self.add_csr_group("drtio", ["drtio0"])
self.add_memory_group("drtio_aux", ["drtio0_aux"]) self.add_memory_group("drtio_aux", ["drtio0_aux"])