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compiler: use correct data layout.

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whitequark 2016-03-31 06:40:25 +00:00
parent c6516f3c83
commit b8bd344e54
1 changed files with 2 additions and 1 deletions
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artiq/compiler/targets.py
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@ -224,6 +224,7 @@ class NativeTarget(Target):
class OR1KTarget(Target):
triple = "or1k-linux"
data_layout = "E-m:e-p:32:32-i64:32-f64:32-v64:32-v128:32-a:0:32-n32"
data_layout = "E-m:e-p:32:32-i8:8:8-i16:16:16-i64:32:32-" \
"f64:32:32-v64:32:32-v128:32:32-a0:0:32-n32"
features = ["mul", "div", "ffl1", "cmov", "addc"]
print_function = "core_log"