mirror of https://github.com/m-labs/artiq.git
libdyld: accept objects with no rela relocations.
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@ -289,7 +289,7 @@ impl<'a> Library<'a> {
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if sym_ent != mem::size_of::<Elf32_Sym>() {
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if sym_ent != mem::size_of::<Elf32_Sym>() {
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return Err("incorrect symbol entry size")?
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return Err("incorrect symbol entry size")?
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}
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}
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if rela_ent != mem::size_of::<Elf32_Rela>() {
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if rela_ent != 0 && rela_ent != mem::size_of::<Elf32_Rela>() {
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return Err("incorrect relocation entry size")?
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return Err("incorrect relocation entry size")?
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}
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}
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