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doc: clarify TTL direction control with buffered cards

This commit is contained in:
Sebastien Bourdeauducq 2019-07-24 10:04:45 +08:00
parent 930291f606
commit b8870997d0
1 changed files with 10 additions and 2 deletions
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12
artiq/coredevice/ttl.py
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@ -138,7 +138,11 @@ class TTLInOut:
cursor. cursor.
There must be a delay of at least one RTIO clock cycle before any There must be a delay of at least one RTIO clock cycle before any
other command can be issued.""" other command can be issued.
This method only configures the direction at the FPGA. When using
buffered I/O interfaces, such as the Sinara TTL cards, the buffer
direction must be configured separately in the hardware."""
self.set_oe(True) self.set_oe(True)
@kernel @kernel
@ -147,7 +151,11 @@ class TTLInOut:
cursor. cursor.
There must be a delay of at least one RTIO clock cycle before any There must be a delay of at least one RTIO clock cycle before any
other command can be issued.""" other command can be issued.
This method only configures the direction at the FPGA. When using
buffered I/O interfaces, such as the Sinara TTL cards, the buffer
direction must be configured separately in the hardware."""
self.set_oe(False) self.set_oe(False)
@kernel @kernel