mirror of https://github.com/m-labs/artiq.git
drtio: add switching input test
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parent
08be176369
commit
b86b6dcc09
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@ -69,11 +69,12 @@ class Testbench:
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self.dut = DUT(2)
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self.dut = DUT(2)
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self.now = 0
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self.now = 0
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def init(self):
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def init(self, with_buffer_space=True):
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yield from self.dut.master.rt_controller.csrs.underflow_margin.write(100)
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yield from self.dut.master.rt_controller.csrs.underflow_margin.write(100)
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while not (yield from self.dut.master.link_layer.rx_up.read()):
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while not (yield from self.dut.master.link_layer.rx_up.read()):
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yield
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yield
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yield from self.get_buffer_space()
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if with_buffer_space:
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yield from self.get_buffer_space()
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def get_buffer_space(self):
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def get_buffer_space(self):
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csrs = self.dut.master.rt_controller.csrs
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csrs = self.dut.master.rt_controller.csrs
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@ -106,13 +107,35 @@ class Testbench:
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if status & 0x4:
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if status & 0x4:
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return "destination unreachable"
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return "destination unreachable"
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def read(self, channel, timeout):
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mcri = self.dut.master.cri
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yield mcri.chan_sel.eq(channel)
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yield mcri.timestamp.eq(timeout)
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yield
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yield mcri.cmd.eq(cri.commands["read"])
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yield
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yield mcri.cmd.eq(cri.commands["nop"])
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yield
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status = yield mcri.i_status
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while status & 0x4:
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yield
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status = yield mcri.i_status
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if status & 0x1:
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return "timeout"
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if status & 0x2:
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return "overflow"
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if status & 0x8:
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return "destination unreachable"
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return ((yield mcri.i_timestamp),
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(yield mcri.i_data))
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class TestSwitching(unittest.TestCase):
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class TestSwitching(unittest.TestCase):
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clocks = {"sys": 8, "rtio": 5, "rtio_rx": 5,
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clocks = {"sys": 8, "rtio": 5, "rtio_rx": 5,
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"rio": 5, "rio_phy": 5,
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"rio": 5, "rio_phy": 5,
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"sys_with_rst": 8, "rtio_with_rst": 5}
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"sys_with_rst": 8, "rtio_with_rst": 5}
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def test_switching(self):
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def test_outputs(self):
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tb = Testbench()
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tb = Testbench()
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def test():
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def test():
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@ -163,3 +186,64 @@ class TestSwitching(unittest.TestCase):
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run_simulation(tb.dut,
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run_simulation(tb.dut,
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{"sys": test(), "rtio": tb.dut.pr.receive(receive), "rtio_rx": send_replies()}, self.clocks)
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{"sys": test(), "rtio": tb.dut.pr.receive(receive), "rtio_rx": send_replies()}, self.clocks)
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def test_inputs(self):
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tb = Testbench()
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def test():
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yield from tb.init(with_buffer_space=False)
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reply = yield from tb.read(19, 145)
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self.assertEqual(reply, (333, 23))
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reply = yield from tb.read(20, 146)
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self.assertEqual(reply, (334, 24))
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reply = yield from tb.read(10, 34)
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self.assertEqual(reply, "timeout")
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reply = yield from tb.read(1, 20)
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self.assertEqual(reply, "overflow")
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reply = yield from tb.read(21, 147)
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self.assertEqual(reply, (335, 25))
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for _ in range(40):
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yield
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current_request = None
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def get_request():
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nonlocal current_request
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while current_request is None:
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yield
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r = current_request
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current_request = None
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return r
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def expect_read(chan_sel, timeout, reply):
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packet_type, field_dict, trailer = yield from get_request()
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self.assertEqual(packet_type, "read_request")
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self.assertEqual(trailer, [])
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self.assertEqual(field_dict["chan_sel"], chan_sel)
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self.assertEqual(field_dict["timeout"], timeout)
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if reply == "timeout":
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yield from tb.dut.pt.send("read_reply_noevent", overflow=0)
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elif reply == "overflow":
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yield from tb.dut.pt.send("read_reply_noevent", overflow=1)
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else:
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timestamp, data = reply
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yield from tb.dut.pt.send("read_reply", timestamp=timestamp, data=data)
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@passive
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def send_replies():
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yield from expect_read(19, 145, (333, 23))
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yield from expect_read(20, 146, (334, 24))
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yield from expect_read(10, 34, "timeout")
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yield from expect_read(1, 20, "overflow")
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yield from expect_read(21, 147, (335, 25))
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unexpected = yield from get_request()
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self.fail("unexpected packet: {}".format(unexpected))
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def receive(packet_type, field_dict, trailer):
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nonlocal current_request
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self.assertEqual(current_request, None)
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current_request = (packet_type, field_dict, trailer)
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run_simulation(tb.dut,
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{"sys": test(), "rtio": tb.dut.pr.receive(receive), "rtio_rx": send_replies()}, self.clocks)
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