From b7a308d33d982cd25c92cf71c7469f3a9ef70f59 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Thu, 8 Dec 2016 17:00:39 +0100 Subject: [PATCH] fir: register multiplier output --- artiq/gateware/dsp/fir.py | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/artiq/gateware/dsp/fir.py b/artiq/gateware/dsp/fir.py index 7893c04bf..6f1535528 100644 --- a/artiq/gateware/dsp/fir.py +++ b/artiq/gateware/dsp/fir.py @@ -47,7 +47,7 @@ class FIR(Module): self.i = Signal((width, True)) self.o = Signal((width, True)) n = len(coefficients) - self.latency = (n + 1)//2 + 1 + self.latency = (n + 1)//2 + 2 ### @@ -55,18 +55,22 @@ class FIR(Module): x = [Signal((width, True)) for _ in range(n)] self.sync += [xi.eq(xj) for xi, xj in zip(x, [self.i] + x)] - # Wire up output + if shift is None: + shift = width - 1 + + # Make products o = [] for i, c in enumerate(coefficients): # simplify for halfband and symmetric filters if c == 0 or c in coefficients[i + 1:]: continue - o.append(c*reduce(add, [ + m = Signal((width + shift, True)) + self.sync += m.eq(c*reduce(add, [ xj for xj, cj in zip(x[::-1], coefficients) if cj == c ])) + o.append(m) - if shift is None: - shift = width - 1 + # Make sum self.sync += self.o.eq(reduce(add, o) >> shift) @@ -85,7 +89,7 @@ class ParallelFIR(Module): # input and output: old to young, decreasing delay self.i = [Signal((width, True)) for i in range(p)] self.o = [Signal((width, True)) for i in range(p)] - self.latency = (n + 1)//2//parallelism + 2 # minus .5 + self.latency = (n + 1)//2//parallelism + 3 # minus one sample ### @@ -96,16 +100,19 @@ class ParallelFIR(Module): if shift is None: shift = width - 1 - # wire up each output for j in range(p): + # Make products o = [] for i, c in enumerate(coefficients): # simplify for halfband and symmetric filters if c == 0 or c in coefficients[i + 1:]: continue - o.append(c*reduce(add, [ + m = Signal((width + shift, True)) + self.sync += m.eq(c*reduce(add, [ xj for xj, cj in zip(x[-1 - j::-1], coefficients) if cj == c ])) + o.append(m) + # Make sum self.sync += self.o[j].eq(reduce(add, o) >> shift)