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https://github.com/m-labs/artiq.git
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aux_controller: multiple receiver buffers
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parent
76d704ac33
commit
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@ -10,6 +10,7 @@ from misoc.interconnect import wishbone
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max_packet = 1024
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aux_buffer_count = 8
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class Transmitter(Module, AutoCSR):
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@ -95,13 +96,13 @@ class Transmitter(Module, AutoCSR):
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class Receiver(Module, AutoCSR):
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def __init__(self, link_layer, min_mem_dw):
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self.aux_rx_length = CSRStatus(bits_for(max_packet))
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self.aux_rx_present = CSR()
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self.aux_rx_error = CSR()
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self.aux_read_pointer = CSR(log2_int(aux_buffer_count))
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ll_dw = len(link_layer.rx_aux_data)
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mem_dw = max(min_mem_dw, ll_dw)
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self.specials.mem = Memory(mem_dw, max_packet//(mem_dw//8))
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self.specials.mem = Memory(mem_dw, aux_buffer_count*max_packet//(mem_dw//8))
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converter = ClockDomainsRenamer("rtio_rx")(
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stream.Converter(ll_dw, mem_dw))
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@ -123,30 +124,45 @@ class Receiver(Module, AutoCSR):
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mem_port = self.mem.get_port(write_capable=True, clock_domain="rtio_rx")
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self.specials += mem_port
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# write pointer represents where the gateware is
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write_pointer = Signal(log2_int(aux_buffer_count))
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write_pointer_sys = Signal.like(write_pointer)
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# read pointer represents where CPU is
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# write reaching read is an error, read reaching write is buffer clear
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read_pointer = Signal.like(write_pointer)
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read_pointer_rx = Signal.like(write_pointer)
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read_pointer.attr.add("no_retiming")
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write_pointer.attr.add("no_retiming")
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signal_error = PulseSynchronizer("rtio_rx", "sys")
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self.specials += [
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MultiReg(read_pointer, read_pointer_rx, "rtio_rx"),
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MultiReg(write_pointer, write_pointer_sys)
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]
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frame_counter_nbits = bits_for(max_packet) - log2_int(mem_dw//8)
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frame_counter = Signal(frame_counter_nbits)
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# frame counter requires one more bit to represent overflow (bits_for)
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# actual valid packet will be addressed with one bit less
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packet_nbits = frame_counter_nbits - 1
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self.comb += [
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mem_port.adr.eq(frame_counter),
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mem_port.adr[:packet_nbits].eq(frame_counter),
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# bits above the frame counter point to current frame
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mem_port.adr[packet_nbits:].eq(write_pointer),
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mem_port.dat_w.eq(converter.source.data),
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converter.source.ack.eq(1)
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converter.source.ack.eq(1),
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self.aux_read_pointer.w.eq(read_pointer)
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]
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frame_counter.attr.add("no_retiming")
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frame_counter_sys = Signal(frame_counter_nbits)
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self.specials += MultiReg(frame_counter, frame_counter_sys)
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self.comb += self.aux_rx_length.status.eq(frame_counter_sys << log2_int(mem_dw//8))
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signal_frame = PulseSynchronizer("rtio_rx", "sys")
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frame_ack = PulseSynchronizer("sys", "rtio_rx")
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signal_error = PulseSynchronizer("rtio_rx", "sys")
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self.submodules += signal_frame, frame_ack, signal_error
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self.submodules += signal_error
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self.sync += [
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If(self.aux_rx_present.re, self.aux_rx_present.w.eq(0)),
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If(signal_frame.o, self.aux_rx_present.w.eq(1)),
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If(self.aux_rx_error.re, self.aux_rx_error.w.eq(0)),
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If(signal_error.o, self.aux_rx_error.w.eq(1))
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If(signal_error.o, self.aux_rx_error.w.eq(1)),
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self.aux_rx_present.w.eq(~(read_pointer == write_pointer_sys)),
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If(self.aux_rx_present.re & self.aux_rx_present.w,
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read_pointer.eq(read_pointer + 1)),
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]
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self.comb += frame_ack.i.eq(self.aux_rx_present.re)
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fsm = ClockDomainsRenamer("rtio_rx")(FSM(reset_state="IDLE"))
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self.submodules += fsm
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@ -171,7 +187,7 @@ class Receiver(Module, AutoCSR):
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NextState("FRAME")
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)
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).Else(
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NextValue(frame_counter, 0)
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NextValue(frame_counter, 0),
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)
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)
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fsm.act("FRAME",
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@ -189,14 +205,12 @@ class Receiver(Module, AutoCSR):
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)
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)
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fsm.act("SIGNAL_FRAME",
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signal_frame.i.eq(1),
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NextState("WAIT_ACK"),
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If(converter.source.stb, signal_error.i.eq(1))
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)
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fsm.act("WAIT_ACK",
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If(frame_ack.o,
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NextValue(frame_counter, 0),
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NextState("IDLE")
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NextState("IDLE"),
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If((write_pointer + 1) == read_pointer_rx,
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# on full buffer, overwrite only current frame
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signal_error.i.eq(1)
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).Else(
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NextValue(write_pointer, write_pointer + 1)
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),
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If(converter.source.stb, signal_error.i.eq(1))
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)
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@ -215,8 +229,8 @@ class DRTIOAuxController(Module):
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tx_sdram_if = wishbone.SRAM(self.transmitter.mem, read_only=False, data_width=dw)
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rx_sdram_if = wishbone.SRAM(self.receiver.mem, read_only=True, data_width=dw)
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decoder = wishbone.Decoder(self.bus,
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[(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus),
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(lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus)],
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[(lambda a: a[log2_int(max_packet*aux_buffer_count)-wsb] == 0, tx_sdram_if.bus),
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(lambda a: a[log2_int(max_packet*aux_buffer_count)-wsb] == 1, rx_sdram_if.bus)],
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register=True)
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self.submodules += tx_sdram_if, rx_sdram_if, decoder
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@ -82,9 +82,10 @@ class Satellite(BaseSoC, AMPSoC):
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core.link_layer, self.cpu_dw))
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self.csr_devices.append("drtioaux0")
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drtio_aux_mem_size = 1024 * 16 # max_packet * 8 buffers * 2 (tx, rx halves)
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memory_address = self.mem_map["drtioaux"]
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self.add_wb_slave(memory_address, 0x800, self.drtioaux0.bus)
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self.add_memory_region("drtioaux0_mem", memory_address | self.shadow_base, 0x800)
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self.add_wb_slave(memory_address, drtio_aux_mem_size, self.drtioaux0.bus)
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self.add_memory_region("drtioaux0_mem", memory_address | self.shadow_base, drtio_aux_mem_size)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtioaux", ["drtioaux0"])
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@ -236,10 +236,11 @@ class MasterBase(MiniSoC, AMPSoC):
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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self.add_wb_slave(memory_address, 0x800,
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drtio_aux_mem_size = 1024 * 16 # max_packet * 8 buffers * 2 (tx, rx halves)
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memory_address = self.mem_map["drtioaux"] + drtio_aux_mem_size*i
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self.add_wb_slave(memory_address, drtio_aux_mem_size,
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coreaux.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, drtio_aux_mem_size)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.config["DRTIO_ROLE"] = "master"
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@ -318,10 +319,11 @@ class MasterBase(MiniSoC, AMPSoC):
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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memory_address = self.mem_map["drtioaux"] + 0x800*channel
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self.add_wb_slave(memory_address, 0x800,
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drtio_aux_mem_size = 1024 * 16 # max_packet * 8 buffers * 2 (tx, rx halves)
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memory_address = self.mem_map["drtioaux"] + drtio_aux_mem_size*channel
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self.add_wb_slave(memory_address, drtio_aux_mem_size,
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coreaux.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, drtio_aux_mem_size)
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def add_drtio_cpuif_groups(self):
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self.add_csr_group("drtio", self.drtio_csr_group)
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@ -486,10 +488,11 @@ class SatelliteBase(BaseSoC, AMPSoC):
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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self.add_wb_slave(memory_address, 0x800,
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drtio_aux_mem_size = 1024 * 16 # max_packet * 8 buffers * 2 (tx, rx halves)
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memory_address = self.mem_map["drtioaux"] + drtio_aux_mem_size * i
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self.add_wb_slave(memory_address, drtio_aux_mem_size,
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coreaux.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, drtio_aux_mem_size)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.config["DRTIO_ROLE"] = "satellite"
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@ -247,10 +247,11 @@ class _MasterBase(MiniSoC, AMPSoC):
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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self.add_wb_slave(memory_address, 0x800,
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drtio_aux_mem_size = 1024 * 16 # max_packet * 8 buffers * 2 (tx, rx halves)
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memory_address = self.mem_map["drtioaux"] + drtio_aux_mem_size*i
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self.add_wb_slave(memory_address, drtio_aux_mem_size,
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coreaux.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, drtio_aux_mem_size)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.add_csr_group("drtio", drtio_csr_group)
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@ -405,10 +406,11 @@ class _SatelliteBase(BaseSoC, AMPSoC):
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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self.add_wb_slave(memory_address, 0x800,
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drtio_aux_mem_size = 1024 * 16 # max_packet * 8 buffers * 2 (tx, rx halves)
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memory_address = self.mem_map["drtioaux"] + drtio_aux_mem_size*i
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self.add_wb_slave(memory_address, drtio_aux_mem_size,
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coreaux.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, drtio_aux_mem_size)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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@ -60,28 +60,36 @@ class TestAuxController(unittest.TestCase):
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while (yield from dut[dw].aux_controller.transmitter.aux_tx.read()):
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yield
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def receive_packet(dw):
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def receive_packet(pkt_no, len, dw):
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while not (yield from dut[dw].aux_controller.receiver.aux_rx_present.read()):
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yield
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length = yield from dut[dw].aux_controller.receiver.aux_rx_length.read()
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p = yield from dut[dw].aux_controller.receiver.aux_read_pointer.read()
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self.assertEqual(pkt_no, p)
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r = []
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for i in range(length//(dw//8)):
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# packet length is derived by software now, so we pass it for the test
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for i in range(len):
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if dw == 64:
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offset = 2048
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if dw == 32:
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offset = 1024
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print(dw)
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max_packet = 1024
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r.append((yield from dut[dw].aux_controller.bus.read(256+i)))
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yield from dut[dw].aux_controller.receiver.aux_rx_present.write(1)
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return r
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prng = random.Random(0)
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def send_and_check_packet(dw):
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def send_and_check_packet(i, dw):
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data = [prng.randrange(2**dw-1) for _ in range(prng.randrange(1, 16))]
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yield from send_packet(data, dw)
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received = yield from receive_packet(dw)
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received = yield from receive_packet(i, len(data), dw)
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self.assertEqual(data, received)
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def sim(dw):
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yield from link_init(dw)
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for i in range(8):
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yield from send_and_check_packet(dw)
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yield from send_and_check_packet(i, dw)
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@passive
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def rt_traffic(dw):
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@ -95,5 +103,5 @@ class TestAuxController(unittest.TestCase):
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yield dut[dw].link_layer.tx_rt_frame.eq(0)
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yield
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run_simulation(dut[32], [sim(32), rt_traffic(32)])
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run_simulation(dut[64], [sim(64), rt_traffic(64)])
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run_simulation(dut[32], [sim(32), rt_traffic(32)], vcd_name="32bit.vcd")
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run_simulation(dut[64], [sim(64), rt_traffic(64)], vcd_name="64bit.vcd")
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