From b5c035bb5207affae54d4e24168790933ab0e9ce Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 23 Jan 2018 13:54:53 +0000 Subject: [PATCH] sayma_rtm: constrain serwb clock input --- artiq/gateware/targets/sayma_rtm.py | 1 + 1 file changed, 1 insertion(+) diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index bbd8fb589..6f7c9ee1c 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -148,6 +148,7 @@ class SaymaRTM(Module): self.submodules += serwb_pll serwb_pads = platform.request("amc_rtm_serwb") + platform.add_period_constraint(serwb_pads.clk_p, 16.) serwb_phy_rtm = serwb.phy.SERWBPHY(platform.device, serwb_pll, serwb_pads, mode="slave") self.submodules.serwb_phy_rtm = serwb_phy_rtm self.comb += self.crg.reset.eq(serwb_phy_rtm.init.reset)