mirror of https://github.com/m-labs/artiq.git
sayma_rtm_drtio: add DDMTD core, move specific cores out of SatelliteBase
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@ -21,6 +21,7 @@ from artiq.gateware.drtio.transceiver import gtp_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.gateware import jesd204_tools
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from artiq.build_soc import add_identifier
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from artiq import __artiq_dir__ as artiq_dir
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@ -78,6 +79,7 @@ class _SatelliteBase(BaseSoC):
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cpu_type="or1k",
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**kwargs)
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add_identifier(self)
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self.rtio_clk_freq = rtio_clk_freq
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platform = self.platform
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@ -159,6 +161,31 @@ class _SatelliteBase(BaseSoC):
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(platform)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
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self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
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self.comb += self.drtiosat.cri.connect(self.local_io.cri)
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class Satellite(_SatelliteBase):
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def __init__(self, **kwargs):
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_SatelliteBase.__init__(self, **kwargs)
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platform = self.platform
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rtio_channels = []
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phy = ttl_serdes_7series.Output_8X(platform.request("allaki0_rfsw0"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = ttl_serdes_7series.Output_8X(platform.request("allaki0_rfsw1"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_rtio(rtio_channels)
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# HMC clock chip and DAC control
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self.comb += [
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platform.request("ad9154_rst_n", 0).eq(1),
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@ -186,28 +213,11 @@ class _SatelliteBase(BaseSoC):
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platform.request("hmc7043_out_en"))
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self.csr_devices.append("hmc7043_out_en")
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
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self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
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self.comb += self.drtiosat.cri.connect(self.local_io.cri)
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class Satellite(_SatelliteBase):
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def __init__(self, **kwargs):
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_SatelliteBase.__init__(self, **kwargs)
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self.rtio_channels = []
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phy = ttl_serdes_7series.Output_8X(self.platform.request("allaki0_rfsw0"))
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = ttl_serdes_7series.Output_8X(self.platform.request("allaki0_rfsw1"))
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_rtio(self.rtio_channels)
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# DDMTD
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# https://github.com/sinara-hw/Sayma_RTM/issues/68
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sysref_pads = platform.request("rtm_fpga_sysref", 1) # use odd-numbered 7043 output
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self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(sysref_pads, self.rtio_clk_freq)
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self.csr_devices.append("sysref_ddmtd")
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class SatmanSoCBuilder(Builder):
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