mirror of https://github.com/m-labs/artiq.git
Globally update UART baudrate to 921600.
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parent
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commit
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@ -57,7 +57,6 @@ mod moninj;
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mod analyzer;
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mod analyzer;
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fn startup() {
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fn startup() {
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board::uart::set_speed(921600);
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board::clock::init();
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board::clock::init();
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info!("ARTIQ runtime starting...");
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info!("ARTIQ runtime starting...");
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info!("software version {}", cfg!(git_describe));
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info!("software version {}", cfg!(git_describe));
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@ -100,7 +100,7 @@ def main():
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logger.info("Booting runtime")
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logger.info("Booting runtime")
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flterm = run_command(
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flterm = run_command(
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"{env} python3 flterm.py {serial} " +
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"{env} python3 flterm.py {serial} --speed 921600" +
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"--kernel /tmp/{tmp}/runtime.bin " +
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"--kernel /tmp/{tmp}/runtime.bin " +
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("--upload-only" if action == "boot" else "--output-only"))
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("--upload-only" if action == "boot" else "--output-only"))
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artiq_flash = run_command(
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artiq_flash = run_command(
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@ -112,6 +112,7 @@ class _NIST_Ions(MiniSoC, AMPSoC):
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sdram_controller_type="minicon",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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l2_size=128*1024,
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ident=artiq_version,
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ident=artiq_version,
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uart_baudrate=921600,
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**kwargs)
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**kwargs)
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AMPSoC.__init__(self)
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AMPSoC.__init__(self)
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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@ -33,6 +33,7 @@ class Master(MiniSoC, AMPSoC):
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sdram_controller_type="minicon",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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l2_size=128*1024,
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ident=artiq_version,
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ident=artiq_version,
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uart_baudrate=921600,
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**kwargs)
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**kwargs)
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AMPSoC.__init__(self)
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AMPSoC.__init__(self)
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@ -131,6 +131,7 @@ class Satellite(BaseSoC):
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sdram_controller_type="minicon",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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l2_size=128*1024,
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ident=artiq_version,
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ident=artiq_version,
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uart_baudrate=921600,
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**kwargs)
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**kwargs)
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platform = self.platform
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platform = self.platform
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@ -169,6 +169,7 @@ class Phaser(MiniSoC, AMPSoC):
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sdram_controller_type="minicon",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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l2_size=128*1024,
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ident=artiq_version,
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ident=artiq_version,
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uart_baudrate=921600,
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**kwargs)
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**kwargs)
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AMPSoC.__init__(self)
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AMPSoC.__init__(self)
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self.platform.toolchain.bitstream_commands.extend([
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self.platform.toolchain.bitstream_commands.extend([
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@ -160,6 +160,7 @@ class Demo(BaseSoC, AMPSoC):
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l2_size=64*1024,
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l2_size=64*1024,
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ident=artiq_version,
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ident=artiq_version,
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clk_freq=75*1000*1000,
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clk_freq=75*1000*1000,
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uart_baudrate=921600,
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**kwargs)
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**kwargs)
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AMPSoC.__init__(self)
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AMPSoC.__init__(self)
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@ -187,7 +187,7 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
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* Check that the board boots by running a serial terminal program (you may need to press its FPGA reconfiguration button or power-cycle it to load the gateware bitstream that was newly written into the flash): ::
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* Check that the board boots by running a serial terminal program (you may need to press its FPGA reconfiguration button or power-cycle it to load the gateware bitstream that was newly written into the flash): ::
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$ flterm /dev/ttyUSB1
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$ flterm /dev/ttyUSB1 --speed 921600
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MiSoC BIOS http://m-labs.hk
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MiSoC BIOS http://m-labs.hk
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[...]
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[...]
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Booting from flash...
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Booting from flash...
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@ -197,7 +197,7 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
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.. note:: flterm is part of MiSoC. If you installed MiSoC with ``setup.py develop --user``, the flterm launcher is in ``~/.local/bin``.
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.. note:: flterm is part of MiSoC. If you installed MiSoC with ``setup.py develop --user``, the flterm launcher is in ``~/.local/bin``.
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The communication parameters are 115200 8-N-1. Ensure that your user has access
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The communication parameters are 921600 8-N-1. Ensure that your user has access
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to the serial device (``sudo adduser $USER dialout`` assuming standard setup).
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to the serial device (``sudo adduser $USER dialout`` assuming standard setup).
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.. _installing-the-host-side-software:
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.. _installing-the-host-side-software:
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