add variant in identifier string

Also add without-sawg suffixes on Sayma.

Closes #1060
Closes #1059

artiq/build_soc.py

@@ -1,12 +1,36 @@
 import os
 import subprocess
 
+from misoc.cores import identifier
 from misoc.integration.builder import *
 
 from artiq.gateware.amp import AMPSoC
+from artiq import __version__ as artiq_version
 from artiq import __artiq_dir__ as artiq_dir
 
 
+__all__ = ["add_identifier", "build_artiq_soc"]
+
+
+def get_identifier_string(soc, suffix="", add_class_name=True):
+    r = artiq_version
+    if suffix or add_class_name:
+        r += ";"
+    if add_class_name:
+        r += soc.__class__.__name__.lower()
+    r += suffix
+    return r
+
+
+def add_identifier(soc, *args, **kwargs):
+    if hasattr(soc, "identifier"):
+        raise ValueError
+    identifier_str = get_identifier_string(soc, *args, **kwargs)
+    soc.submodules.identifier = identifier.Identifier(identifier_str)
+    soc.config["IDENTIFIER_STR"] = identifier_str
+
+
+
 def build_artiq_soc(soc, argdict):
     firmware_dir = os.path.join(artiq_dir, "firmware")
     builder = Builder(soc, **argdict)

artiq/coredevice/comm_kernel.py

@@ -220,7 +220,7 @@ class CommKernel:
             raise UnsupportedDevice("Unsupported runtime ID: {}"
                                     .format(runtime_id))
 
-        gateware_version = self._read_string()
+        gateware_version = self._read_string().split(";")[0]
         if gateware_version != software_version and not self.warned_of_mismatch:
             logger.warning("Mismatch between gateware (%s) "
                            "and software (%s) versions",

artiq/firmware/Cargo.lock

@@ -13,7 +13,6 @@ version = "0.0.0"
 dependencies = [
  "bitflags 1.0.3 (registry+https://github.com/rust-lang/crates.io-index)",
  "board_misoc 0.0.0",
- "build_artiq 0.0.0",
  "build_misoc 0.0.0",
  "byteorder 1.2.3 (registry+https://github.com/rust-lang/crates.io-index)",
  "crc 1.8.1 (registry+https://github.com/rust-lang/crates.io-index)",
@@ -47,13 +46,6 @@ dependencies = [
  "smoltcp 0.4.0 (git+https://github.com/m-labs/smoltcp?rev=181083f)",
 ]
 
-[[package]]
-name = "build_artiq"
-version = "0.0.0"
-dependencies = [
- "walkdir 1.0.7 (registry+https://github.com/rust-lang/crates.io-index)",
-]
-
 [[package]]
 name = "build_const"
 version = "0.2.1"
@@ -224,7 +216,6 @@ dependencies = [
  "alloc_list 0.0.0",
  "board_artiq 0.0.0",
  "board_misoc 0.0.0",
- "build_artiq 0.0.0",
  "build_misoc 0.0.0",
  "byteorder 1.2.3 (registry+https://github.com/rust-lang/crates.io-index)",
  "cslice 0.3.0 (registry+https://github.com/rust-lang/crates.io-index)",
@@ -255,7 +246,6 @@ version = "0.0.0"
 dependencies = [
  "board_artiq 0.0.0",
  "board_misoc 0.0.0",
- "build_artiq 0.0.0",
  "build_misoc 0.0.0",
  "log 0.4.1 (registry+https://github.com/rust-lang/crates.io-index)",
 ]

artiq/firmware/libboard_artiq/Cargo.toml

@@ -10,7 +10,6 @@ path = "lib.rs"
 
 [build-dependencies]
 build_misoc = { path = "../libbuild_misoc" }
-build_artiq = { path = "../libbuild_artiq" }
 
 [dependencies]
 failure = { version = "0.1", default-features = false }

artiq/firmware/libbuild_artiq/Cargo.toml

@@ -1,11 +0,0 @@
-[package]
-authors = ["M-Labs"]
-name = "build_artiq"
-version = "0.0.0"
-
-[lib]
-name = "build_artiq"
-path = "lib.rs"
-
-[dependencies]
-walkdir = "1.0"

artiq/firmware/libbuild_artiq/lib.rs

@@ -1,45 +0,0 @@
-extern crate walkdir;
-
-use std::env;
-use std::fs;
-use std::path::Path;
-use std::process::Command;
-
-use walkdir::WalkDir;
-
-pub fn git_describe() {
-    let git_checkout = Path::new("../../..");
-    for entry in WalkDir::new(git_checkout) {
-        let entry = entry.unwrap();
-        println!("cargo:rerun-if-changed={}", entry.path().display());
-    }
-
-    let version;
-    if git_checkout.join(".git").exists() {
-        let git_describe =
-            Command::new("git")
-                    .arg("describe")
-                    .arg("--tags")
-                    .arg("--dirty")
-                    .arg("--always")
-                    .arg("--long")
-                    .arg("--abbrev=8")
-                    .output()
-                    .ok()
-                    .and_then(|o| String::from_utf8(o.stdout).ok())
-                    .map(|mut s| {
-                        let len = s.trim_right().len();
-                        s.truncate(len);
-                        s
-                    })
-                    .unwrap();
-        let parts = git_describe.split("-").collect::<Vec<_>>();
-        version = format!("{}+{}.{}", parts[0], parts[1], parts[2]);
-    } else {
-        version = "unknown".to_owned();
-    }
-
-    let out_dir = env::var("OUT_DIR").unwrap();
-    let git_describe = Path::new(&out_dir).join("git-describe");
-    fs::write(&git_describe, version).unwrap();
-}

artiq/firmware/runtime/Cargo.toml

@@ -11,7 +11,6 @@ path = "main.rs"
 
 [build-dependencies]
 build_misoc = { path = "../libbuild_misoc" }
-build_artiq = { path = "../libbuild_artiq" }
 
 [dependencies]
 failure = { version = "0.1", default-features = false }

artiq/firmware/runtime/build.rs

@@ -1,7 +1,5 @@
 extern crate build_misoc;
-extern crate build_artiq;
 
 fn main() {
     build_misoc::cfg();
-    build_artiq::git_describe();
 }

artiq/firmware/runtime/main.rs

@@ -66,7 +66,7 @@ fn startup() {
     irq::set_ie(true);
     clock::init();
     info!("ARTIQ runtime starting...");
-    info!("software version {}", include_str!(concat!(env!("OUT_DIR"), "/git-describe")));
+    info!("software version {}", csr::CONFIG_IDENTIFIER_STR);
     info!("gateware version {}", ident::read(&mut [0; 64]));
 
     match config::read_str("log_level", |r| r.map(|s| s.parse())) {
@@ -355,8 +355,7 @@ pub extern fn panic_fmt(args: core::fmt::Arguments, file: &'static str,
 
     println!("panic at {}:{}:{}: {}", file, line, column, args);
 
-    println!("backtrace for software version {}:",
+    println!("backtrace for software version {}:", csr::CONFIG_IDENTIFIER_STR);
-             include_str!(concat!(env!("OUT_DIR"), "/git-describe")));
     let _ = unwind_backtrace::backtrace(|ip| {
         // Backtrace gives us the return address, i.e. the address after the delay slot,
         // but we're interested in the call instruction.

artiq/firmware/satman/Cargo.toml

@@ -11,7 +11,6 @@ path = "main.rs"
 
 [build-dependencies]
 build_misoc = { path = "../libbuild_misoc" }
-build_artiq = { path = "../libbuild_artiq" }
 
 [dependencies]
 log = { version = "0.4", default-features = false }

artiq/firmware/satman/build.rs

@@ -1,7 +1,5 @@
 extern crate build_misoc;
-extern crate build_artiq;
 
 fn main() {
     build_misoc::cfg();
-    build_artiq::git_describe();
 }

artiq/firmware/satman/main.rs

@@ -260,7 +260,7 @@ pub extern fn main() -> i32 {
     uart_logger::ConsoleLogger::register();
 
     info!("ARTIQ satellite manager starting...");
-    info!("software version {}", include_str!(concat!(env!("OUT_DIR"), "/git-describe")));
+    info!("software version {}", csr::CONFIG_IDENTIFIER_STR);
     info!("gateware version {}", ident::read(&mut [0; 64]));
 
     #[cfg(has_slave_fpga_cfg)]

artiq/gateware/targets/kasli.py

@@ -22,8 +22,7 @@ from artiq.gateware.drtio.transceiver import gtp_7series
 from artiq.gateware.drtio.siphaser import SiPhaser7Series
 from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
 from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite
-from artiq.build_soc import build_artiq_soc
+from artiq.build_soc import *
-from artiq import __version__ as artiq_version
 
 
 class _RTIOCRG(Module, AutoCSR):
@@ -100,11 +99,11 @@ class _StandaloneBase(MiniSoC, AMPSoC):
                          cpu_type="or1k",
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
-                         ident=artiq_version,
                          ethmac_nrxslots=4,
                          ethmac_ntxslots=4,
                          **kwargs)
         AMPSoC.__init__(self)
+        add_identifier(self)
 
         self.submodules.leds = gpio.GPIOOut(Cat(
             self.platform.request("user_led", 0)))
@@ -622,11 +621,11 @@ class _MasterBase(MiniSoC, AMPSoC):
                          cpu_type="or1k",
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
-                         ident=artiq_version,
                          ethmac_nrxslots=4,
                          ethmac_ntxslots=4,
                          **kwargs)
         AMPSoC.__init__(self)
+        add_identifier(self)
 
         platform = self.platform
         rtio_clk_freq = 150e6
@@ -754,8 +753,8 @@ class _SatelliteBase(BaseSoC):
                  cpu_type="or1k",
                  sdram_controller_type="minicon",
                  l2_size=128*1024,
-                 ident=artiq_version,
                  **kwargs)
+        add_identifier(self)
 
         platform = self.platform
         rtio_clk_freq = 150e6

artiq/gateware/targets/kc705.py

@@ -18,8 +18,7 @@ from artiq.gateware.amp import AMPSoC
 from artiq.gateware import rtio, nist_clock, nist_qc2
 from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
                                      dds, spi2, ad53xx_monitor)
-from artiq.build_soc import build_artiq_soc
+from artiq.build_soc import *
-from artiq import __version__ as artiq_version
 
 
 class _RTIOCRG(Module, AutoCSR):
@@ -219,11 +218,12 @@ class _StandaloneBase(MiniSoC, AMPSoC):
                          cpu_type="or1k",
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
-                         ident=artiq_version,
                          ethmac_nrxslots=4,
                          ethmac_ntxslots=4,
                          **kwargs)
         AMPSoC.__init__(self)
+        add_identifier(self)
+
         if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
             self.platform.toolchain.bitstream_commands.extend([
                 "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",

artiq/gateware/targets/sayma_amc.py

@@ -22,8 +22,7 @@ from artiq.gateware.drtio.transceiver import gth_ultrascale
 from artiq.gateware.drtio.siphaser import SiPhaser7Series
 from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
 from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite
-from artiq.build_soc import build_artiq_soc
+from artiq.build_soc import *
-from artiq import __version__ as artiq_version
 
 
 class AD9154(Module, AutoCSR):
@@ -132,12 +131,12 @@ class Standalone(MiniSoC, AMPSoC, RTMCommon):
                          cpu_type="or1k",
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
-                         ident=artiq_version,
                          ethmac_nrxslots=4,
                          ethmac_ntxslots=4,
                          **kwargs)
         AMPSoC.__init__(self)
         RTMCommon.__init__(self)
+        add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
         self.config["HMC830_REF"] = "100"
 
         platform = self.platform
@@ -238,12 +237,12 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
                          cpu_type="or1k",
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
-                         ident=artiq_version,
                          ethmac_nrxslots=4,
                          ethmac_ntxslots=4,
                          **kwargs)
         AMPSoC.__init__(self)
         RTMCommon.__init__(self)
+        add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
         self.config["HMC830_REF"] = "100"
 
         platform = self.platform
@@ -385,11 +384,11 @@ class Master(MiniSoC, AMPSoC):
                          cpu_type="or1k",
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
-                         ident=artiq_version,
                          ethmac_nrxslots=4,
                          ethmac_ntxslots=4,
                          **kwargs)
         AMPSoC.__init__(self)
+        add_identifier(self)
 
         platform = self.platform
         rtio_clk_freq = 150e6
@@ -504,9 +503,9 @@ class Satellite(BaseSoC, RTMCommon):
                  cpu_type="or1k",
                  sdram_controller_type="minicon",
                  l2_size=128*1024,
-                 ident=artiq_version,
                  **kwargs)
         RTMCommon.__init__(self)
+        add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
         self.config["HMC830_REF"] = "150"
 
         platform = self.platform