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https://github.com/m-labs/artiq.git
synced 2024-12-28 20:53:35 +08:00
netboot: support slave FPGA loading
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parent
307f39e900
commit
b25a17fa37
@ -140,15 +140,14 @@ fn load_slave_fpga() {
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println!(" ...Error during loading: {}", e);
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return
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}
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if let Err(e) = slave_fpga::complete() {
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println!(" ...Error during completion: {}", e);
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if let Err(e) = slave_fpga::startup() {
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println!(" ...Error during startup: {}", e);
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return
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}
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println!(" ...done");
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}
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fn flash_boot() {
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const FIRMWARE: *mut u8 = board_mem::FLASH_BOOT_ADDRESS as *mut u8;
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const MAIN_RAM: *mut u8 = board_mem::MAIN_RAM_BASE as *mut u8;
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@ -193,8 +192,16 @@ enum NetConnState {
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WaitCommand,
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FirmwareLength(usize, u8),
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FirmwareDownload(usize, usize),
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WaitO,
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WaitK
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FirmwareWaitO,
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FirmwareWaitK,
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#[cfg(has_slave_fpga_cfg)]
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GatewareLength(usize, u8),
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#[cfg(has_slave_fpga_cfg)]
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GatewareDownload(usize, usize),
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#[cfg(has_slave_fpga_cfg)]
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GatewareWaitO,
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#[cfg(has_slave_fpga_cfg)]
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GatewareWaitK
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}
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#[cfg(has_ethmac)]
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@ -228,6 +235,12 @@ impl NetConn {
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self.state = NetConnState::FirmwareLength(0, 0);
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Ok(1)
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},
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#[cfg(has_slave_fpga_cfg)]
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b'G' => {
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println!("Received gateware load command");
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self.state = NetConnState::GatewareLength(0, 0);
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Ok(1)
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}
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b'B' => {
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if self.firmware_downloaded {
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println!("Received boot command");
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@ -245,6 +258,7 @@ impl NetConn {
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}
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}
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},
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NetConnState::FirmwareLength(firmware_length, recv_bytes) => {
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let firmware_length = (firmware_length << 8) | (buf[0] as usize);
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let recv_bytes = recv_bytes + 1;
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@ -269,23 +283,23 @@ impl NetConn {
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let recv_bytes = recv_bytes + length;
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if recv_bytes == firmware_length {
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self.state = NetConnState::WaitO;
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self.state = NetConnState::FirmwareWaitO;
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Ok(length)
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} else {
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self.state = NetConnState::FirmwareDownload(firmware_length, recv_bytes);
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Ok(length)
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}
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},
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NetConnState::WaitO => {
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NetConnState::FirmwareWaitO => {
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if buf[0] == b'O' {
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self.state = NetConnState::WaitK;
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self.state = NetConnState::FirmwareWaitK;
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Ok(1)
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} else {
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println!("End-of-firmware confirmation failed");
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Err(())
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}
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},
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NetConnState::WaitK => {
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NetConnState::FirmwareWaitK => {
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if buf[0] == b'K' {
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println!("Firmware successfully downloaded");
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self.state = NetConnState::WaitCommand;
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@ -296,6 +310,71 @@ impl NetConn {
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Err(())
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}
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}
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#[cfg(has_slave_fpga_cfg)]
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NetConnState::GatewareLength(gateware_length, recv_bytes) => {
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let gateware_length = (gateware_length << 8) | (buf[0] as usize);
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let recv_bytes = recv_bytes + 1;
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if recv_bytes == 4 {
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if let Err(e) = slave_fpga::prepare() {
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println!(" Error during slave FPGA preparation: {}", e);
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return Err(())
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}
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self.state = NetConnState::GatewareDownload(gateware_length, 0);
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} else {
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self.state = NetConnState::GatewareLength(gateware_length, recv_bytes);
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}
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Ok(1)
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},
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#[cfg(has_slave_fpga_cfg)]
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NetConnState::GatewareDownload(gateware_length, recv_bytes) => {
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let max_length = gateware_length - recv_bytes;
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let buf = if buf.len() > max_length {
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&buf[..max_length]
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} else {
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&buf[..]
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};
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let length = buf.len();
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if let Err(e) = slave_fpga::input(buf) {
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println!("Error during slave FPGA loading: {}", e);
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return Err(())
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}
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let recv_bytes = recv_bytes + length;
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if recv_bytes == gateware_length {
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self.state = NetConnState::GatewareWaitO;
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Ok(length)
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} else {
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self.state = NetConnState::GatewareDownload(gateware_length, recv_bytes);
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Ok(length)
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}
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},
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#[cfg(has_slave_fpga_cfg)]
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NetConnState::GatewareWaitO => {
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if buf[0] == b'O' {
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self.state = NetConnState::GatewareWaitK;
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Ok(1)
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} else {
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println!("End-of-gateware confirmation failed");
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Err(())
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}
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},
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#[cfg(has_slave_fpga_cfg)]
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NetConnState::GatewareWaitK => {
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if buf[0] == b'K' {
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if let Err(e) = slave_fpga::startup() {
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println!("Error during slave FPGA startup: {}", e);
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return Err(())
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}
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println!("Gateware successfully downloaded");
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self.state = NetConnState::WaitCommand;
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Ok(1)
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} else {
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println!("End-of-gateware confirmation failed");
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Err(())
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}
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}
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}
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}
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@ -59,7 +59,7 @@ pub fn input(data: &[u8]) -> Result<(), &'static str> {
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Ok(())
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}
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pub fn complete() -> Result<(), &'static str> {
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pub fn startup() -> Result<(), &'static str> {
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unsafe {
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let t = clock::get_ms();
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while csr::slave_fpga_cfg::in_read() & DONE_BIT == 0 {
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@ -5,12 +5,29 @@ import socket
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import struct
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import os
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def send_file(sock, filename):
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with open(filename, "rb") as input_file:
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sock.sendall(struct.pack(">I", os.fstat(input_file.fileno()).st_size))
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while True:
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data = input_file.read(4096)
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if not data:
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break
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sock.sendall(data)
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sock.sendall(b"OK")
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def main():
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parser = argparse.ArgumentParser(description="ARTIQ netboot tool")
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parser.add_argument("hostname", metavar="HOSTNAME",
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help="hostname of the target board")
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parser.add_argument("-f", "--firmware", nargs=1,
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help="firmware to load")
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# Note that on softcore systems, the main gateware cannot be replaced
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# with -g. This option is used for loading the RTM FPGA from the AMC
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# on Sayma, and the PL on Zynq.
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parser.add_argument("-g", "--gateware", nargs=1,
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help="gateware to load")
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parser.add_argument("-b", "--boot", action="store_true",
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help="boot the device")
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args = parser.parse_args()
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@ -18,15 +35,11 @@ def main():
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sock = socket.create_connection((args.hostname, 4269))
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try:
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if args.firmware is not None:
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with open(args.firmware[0], "rb") as input_file:
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sock.sendall(b"F")
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sock.sendall(struct.pack(">I", os.fstat(input_file.fileno()).st_size))
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while True:
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data = input_file.read(4096)
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if not data:
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break
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sock.sendall(data)
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sock.sendall(b"OK")
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sock.sendall(b"F")
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send_file(sock, args.firmware[0])
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if args.gateware is not None:
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sock.sendall(b"G")
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send_file(sock, args.gateware[0])
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if args.boot:
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sock.sendall(b"B")
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finally:
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