diff --git a/soc/artiqlib/rtio/core.py b/soc/artiqlib/rtio/core.py
index 0f6ad2e8b..3c7d44d27 100644
--- a/soc/artiqlib/rtio/core.py
+++ b/soc/artiqlib/rtio/core.py
@@ -172,7 +172,6 @@ class RTIO(Module, AutoCSR):
 
         self._r_counter = CSRStatus(counter_width+fine_ts_width)
         self._r_counter_update = CSR()
-        self._r_ise_workaround = CSRStatus(32) # FIXME: remove this
 
         # Counter
         self.sync += \