mirror of https://github.com/m-labs/artiq.git
test: set uart log level to INFO for DMA tests
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@ -652,6 +652,18 @@ class _DMA(EnvExperiment):
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class DMATest(ExperimentCase):
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def setUp(self):
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super().setUp()
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# prevent DEBUG log messages causing delay for DMA
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core_addr = self.device_mgr.get_desc("core")["arguments"]["host"]
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self.mgmt = CommMgmt(core_addr)
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self.mgmt.set_uart_log_level('INFO')
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def tearDown(self):
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self.mgmt.set_uart_log_level('DEBUG')
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self.mgmt.close()
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super().tearDown()
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def test_dma_storage(self):
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exp = self.create(_DMA)
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exp.record()
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