mirror of https://github.com/m-labs/artiq.git
drop SI5324_SAYMA_REF
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parent
995a4428e7
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b04e15741b
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@ -138,7 +138,7 @@ fn startup() {
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fn setup_si5324_as_synthesizer()
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{
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// 125MHz output, from 100MHz CLKIN2 reference, 586 Hz loop bandwidth
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#[cfg(all(not(si5324_sayma_ref), rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "100.0"))]
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#[cfg(all(rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "100.0"))]
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const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
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= board_artiq::si5324::FrequencySettings {
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n1_hs : 10,
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@ -151,7 +151,7 @@ fn setup_si5324_as_synthesizer()
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crystal_ref: false
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};
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// 125MHz output, from 125MHz CLKIN2 reference, 606 Hz loop bandwidth
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#[cfg(all(not(si5324_sayma_ref), rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "125.0"))]
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#[cfg(all(rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "125.0"))]
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const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
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= board_artiq::si5324::FrequencySettings {
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n1_hs : 5,
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@ -164,7 +164,7 @@ fn setup_si5324_as_synthesizer()
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crystal_ref: false
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};
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// 125MHz output, from crystal, 7 Hz
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#[cfg(all(not(si5324_sayma_ref), rtio_frequency = "125.0", not(si5324_ext_ref)))]
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#[cfg(all(rtio_frequency = "125.0", not(si5324_ext_ref)))]
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const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
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= board_artiq::si5324::FrequencySettings {
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n1_hs : 10,
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@ -177,7 +177,7 @@ fn setup_si5324_as_synthesizer()
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crystal_ref: true
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};
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// 150MHz output, from crystal
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#[cfg(all(not(si5324_sayma_ref), rtio_frequency = "150.0", not(si5324_ext_ref)))]
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#[cfg(all(rtio_frequency = "150.0", not(si5324_ext_ref)))]
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const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
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= board_artiq::si5324::FrequencySettings {
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n1_hs : 9,
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@ -190,7 +190,7 @@ fn setup_si5324_as_synthesizer()
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crystal_ref: true
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};
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// 100MHz output, from crystal. Also used as reference for Sayma HMC830.
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#[cfg(any(si5324_sayma_ref, all(rtio_frequency = "100.0", not(si5324_ext_ref))))]
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#[cfg(all(rtio_frequency = "100.0", not(si5324_ext_ref)))]
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const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
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= board_artiq::si5324::FrequencySettings {
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n1_hs : 9,
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@ -151,7 +151,6 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["SI5324_SAYMA_REF"] = None
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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# ensure pins are properly biased and terminated
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si5324_clkout = platform.request("cdr_clk_clean", 0)
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