diff --git a/artiq/examples/phaser/startup_kernel.py b/artiq/examples/phaser/startup_kernel.py
index 2357b9fc9..ecc31cd2a 100644
--- a/artiq/examples/phaser/startup_kernel.py
+++ b/artiq/examples/phaser/startup_kernel.py
@@ -1,3 +1,5 @@
+from math import ceil
+
 from artiq.experiment import *
 from artiq.coredevice.ad9516_reg import *
 
@@ -47,9 +49,11 @@ class StartupKernel(EnvExperiment):
         self.ad9154.clock_write(AD9516_OUT1, 0*AD9516_OUT1_POWER_DOWN |
                 2*AD9516_OUT1_LVPECLDIFFERENTIAL_VOLTAGE)
 
-        # FPGA deviceclk, dclk/1
-        self.ad9154.clock_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_1 |
-                AD9516_DIVIDER_4_BYPASS_2)
+        # FPGA deviceclk, dclk/4
+        self.ad9154.clock_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_2)
+        self.ad9154.clock_write(AD9516_DIVIDER_0_0,
+            (ceil(4/2)-1)*AD9516_DIVIDER_0_HIGH_CYCLES |
+            (4//2-1)*AD9516_DIVIDER_0_LOW_CYCLES)
         self.ad9154.clock_write(AD9516_DIVIDER_4_4, 1*AD9516_DIVIDER_4_DCCOFF)
         self.ad9154.clock_write(AD9516_OUT9, 1*AD9516_OUT9_LVDS_OUTPUT_CURRENT |
                 2*AD9516_OUT9_LVDS_CMOS_OUTPUT_POLARITY |
diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
index d517756cc..ee6b87b1c 100755
--- a/artiq/gateware/targets/kc705.py
+++ b/artiq/gateware/targets/kc705.py
@@ -460,7 +460,7 @@ class AD9154(Module, AutoCSR):
         ts = JESD204BTransportSettings(f=2, s=1, k=16, cs=1)
         jesd_settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
         jesd_linerate = 5e9
-        jesd_refclk_freq = 500e6
+        jesd_refclk_freq = 125e6
         rtio_freq = 125*1000*1000
         jesd_phys = [JESD204BPhyTX(
             rtio_crg.refclk, jesd_refclk_freq,