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sayma: instantiate dummy IBUFDS_GTE3 on unused but driven Si5324 clock pins

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Solve same problem as e83ee3a0 but channels cannot be independently disabled.
This commit is contained in:
Sebastien Bourdeauducq 2018-08-05 23:02:41 +08:00
parent e83ee3a07a
commit b023865b42
1 changed files with 15 additions and 0 deletions
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15
artiq/gateware/targets/sayma_amc.py
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@ -151,6 +151,11 @@ class Standalone(MiniSoC, AMPSoC, RTMCommon):
self.config["HAS_SI5324"] = None self.config["HAS_SI5324"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["SI5324_SAYMA_REF"] = None self.config["SI5324_SAYMA_REF"] = None
# ensure pins are properly biased and terminated
si5324_clkout = platform.request("si5324_clkout", 0)
self.specials += Instance(
"IBUFDS_GTE3", i_CEB=0, i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
attr={("DONT_TOUCH", "true")})
# RTIO # RTIO
rtio_channels = [] rtio_channels = []
@ -258,6 +263,11 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
self.config["HAS_SI5324"] = None self.config["HAS_SI5324"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["SI5324_SAYMA_REF"] = None self.config["SI5324_SAYMA_REF"] = None
# ensure pins are properly biased and terminated
si5324_clkout = platform.request("si5324_clkout", 0)
self.specials += Instance(
"IBUFDS_GTE3", i_CEB=0, i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
attr={("DONT_TOUCH", "true")})
self.comb += [ self.comb += [
platform.request("sfp_tx_disable", i).eq(0) platform.request("sfp_tx_disable", i).eq(0)
@ -603,6 +613,11 @@ class Satellite(BaseSoC, RTMCommon):
self.csr_devices.append("i2c") self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1 self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None self.config["HAS_SI5324"] = None
# ensure pins are properly biased and terminated
si5324_clkout = platform.request("si5324_clkout", 0)
self.specials += Instance(
"IBUFDS_GTE3", i_CEB=0, i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
attr={("DONT_TOUCH", "true")})
self.submodules.sysref_sampler = jesd204_tools.SysrefSampler( self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
self.drtio0.coarse_ts, self.ad9154_crg.jref) self.drtio0.coarse_ts, self.ad9154_crg.jref)