get frequency from RTIO, support fractional frequencies

artiq/devices/corecom_serial.py

@@ -3,9 +3,9 @@ import termios
 import struct
 import zlib
 from enum import Enum
+from fractions import Fraction
 import logging
 
-from artiq.language import units
 from artiq.language import core as core_language
 from artiq.devices.runtime import Environment
 from artiq.devices import runtime_exceptions
@@ -123,9 +123,11 @@ class CoreCom:
             runtime_id += chr(reply)
         if runtime_id != "AROR":
             raise UnsupportedDevice("Unsupported runtime ID: "+runtime_id)
-        (ref_period, ) = struct.unpack(">l", _read_exactly(self.port, 4))
-        logger.debug("Environment ref_period: {}".format(ref_period))
-        return Environment(ref_period*units.ps)
+        (ref_freq_i, ref_freq_fn, ref_freq_fd) = struct.unpack(
+            ">lBB", _read_exactly(self.port, 6))
+        ref_period = 1/(ref_freq_i + Fraction(ref_freq_fn, ref_freq_fd))
+        logger.debug("environment ref_period: {}".format(ref_period))
+        return Environment(ref_period)
 
     def load(self, kcode):
         _write_exactly(self.port, struct.pack(

artiq/transforms/lower_units.py

@@ -40,4 +40,4 @@ class _UnitsLowerer(ast.NodeTransformer):
 
 
 def lower_units(func_def, ref_period):
-    _UnitsLowerer(ref_period.amount).visit(func_def)
+    _UnitsLowerer(ref_period).visit(func_def)

soc/artiqlib/rtio/core.py

@@ -1,3 +1,5 @@
+from fractions import Fraction
+
 from migen.fhdl.std import *
 from migen.bank.description import *
 from migen.genlib.fifo import SyncFIFO
@@ -138,7 +140,7 @@ class _RTIOBankI(Module):
 
 
 class RTIO(Module, AutoCSR):
-    def __init__(self, phy, counter_width=32, ofifo_depth=64, ififo_depth=64):
+    def __init__(self, phy, clk_freq, counter_width=32, ofifo_depth=64, ififo_depth=64):
         fine_ts_width = get_fine_ts_width(phy.rbus)
 
         # Submodules
@@ -173,12 +175,9 @@ class RTIO(Module, AutoCSR):
         self._r_counter = CSRStatus(counter_width+fine_ts_width)
         self._r_counter_update = CSR()
 
-        # Counter
-        self.sync += \
-           If(self._r_counter_update.re,
-               self._r_counter.status.eq(Cat(Replicate(0, fine_ts_width),
-                                             self.bank_o.counter))
-           )
+        self._r_frequency_i = CSRStatus(32)
+        self._r_frequency_fn = CSRStatus(8)
+        self._r_frequency_fd = CSRStatus(8)
 
         # OE
         oes = []
@@ -217,3 +216,20 @@ class RTIO(Module, AutoCSR):
             self._r_i_error.status.eq(
                 Cat(self.bank_i.overflow, self.bank_i.pileup))
         ]
+
+        # Counter
+        self.sync += \
+           If(self._r_counter_update.re,
+               self._r_counter.status.eq(Cat(Replicate(0, fine_ts_width),
+                                             self.bank_o.counter))
+           )
+
+        # Frequency
+        clk_freq = Fraction(clk_freq).limit_denominator(255)
+        clk_freq_i = int(clk_freq)
+        clk_freq_f = clk_freq - clk_freq_i
+        self.comb += [
+            self._r_frequency_i.status.eq(clk_freq_i),
+            self._r_frequency_fn.status.eq(clk_freq_f.numerator),
+            self._r_frequency_fd.status.eq(clk_freq_f.denominator)
+        ]

soc/runtime/corecom_serial.c

@@ -154,7 +154,9 @@ void corecom_serve(object_loader load_object, kernel_runner run_kernel)
         if(msgtype == MSGTYPE_REQUEST_IDENT) {
             send_char(MSGTYPE_IDENT);
             send_int(0x41524f52); /* "AROR" - ARTIQ runtime on OpenRISC */
-            send_int(1000000000000LL/identifier_frequency_read()); /* RTIO clock period in picoseconds */
+            send_int(rtio_frequency_i_read());
+            send_char(rtio_frequency_fn_read());
+            send_char(rtio_frequency_fd_read());
         } else if(msgtype == MSGTYPE_LOAD_OBJECT)
             receive_and_load_object(load_object);
         else if(msgtype == MSGTYPE_RUN_KERNEL)

soc/targets/artiq.py

@@ -61,7 +61,7 @@ class ARTIQMiniSoC(BaseSoC):
             rtio_pads,
             output_only_pads={rtio_pads[1], rtio_pads[2], rtio_pads[3]},
             mini_pads={fud})
-        self.submodules.rtio = rtio.RTIO(self.rtiophy)
+        self.submodules.rtio = rtio.RTIO(self.rtiophy, self.clk_freq)
 
         if with_test_gen:
             self.submodules.test_gen = _TestGen(platform.request("ttl", 4))