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gateware: use default MiSoC timer

This commit is contained in:
Sebastien Bourdeauducq 2017-01-18 15:22:33 -06:00
parent b4f3be7e1b
commit aeb1ba8471
1 changed files with 2 additions and 8 deletions
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10
artiq/gateware/soc.py
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@ -10,19 +10,13 @@ from artiq import __artiq_dir__ as artiq_dir
class AMPSoC: class AMPSoC:
"""Contains timer, kernel CPU and mailbox for ARTIQ SoCs. """Contains kernel CPU and mailbox for ARTIQ SoCs.
Users must disable the timer from the platform SoC and provide Users must provide a "mailbox" entry in the memory map.
a "mailbox" entry in the memory map.
""" """
def __init__(self): def __init__(self):
if not hasattr(self, "cpu"): if not hasattr(self, "cpu"):
raise ValueError("Platform SoC must be initialized first") raise ValueError("Platform SoC must be initialized first")
if hasattr(self, "timer0"):
raise ValueError("Timer already exists. "
"Initialize platform SoC using with_timer=False")
self.submodules.timer0 = timer.Timer(width=64)
self.submodules.kernel_cpu = amp.KernelCPU(self.platform) self.submodules.kernel_cpu = amp.KernelCPU(self.platform)
self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram) self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram)