mirror of https://github.com/m-labs/artiq.git
gateware.pipistrello: use pmod for spi
This commit is contained in:
parent
e7146cc999
commit
ade3eda19a
|
@ -152,8 +152,8 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
|
|||
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512,
|
||||
ofifo_depth=4))
|
||||
|
||||
# the last five ttls are used for SPI and a ClockGen
|
||||
for i in range(11):
|
||||
# the last TTL is used for ClockGen
|
||||
for i in range(15):
|
||||
if i in (0, 1):
|
||||
phy = ttl_serdes_spartan6.Output_4X(platform.request("ttl", i),
|
||||
self.rtio_crg.rtiox4_stb)
|
||||
|
@ -192,15 +192,12 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
|
|||
ofifo_depth=512,
|
||||
ififo_depth=4))
|
||||
|
||||
spi_pins = Record([("cs_n", 1), ("clk", 1), ("mosi", 1), ("miso", 1)])
|
||||
# cs_n can be multiple bits wide, one-hot
|
||||
# absence of miso indicates bidirectional mosi
|
||||
self.comb += [
|
||||
platform.request("ttl", 11).eq(spi_pins.cs_n),
|
||||
platform.request("ttl", 12).eq(spi_pins.clk),
|
||||
platform.request("ttl", 13).eq(spi_pins.mosi),
|
||||
spi_pins.miso.eq(platform.request("ttl", 14)),
|
||||
]
|
||||
pmod = self.platform.request("pmod", 0)
|
||||
spi_pins = Module()
|
||||
spi_pins.clk = pmod.d[0]
|
||||
spi_pins.mosi = pmod.d[1]
|
||||
spi_pins.miso = pmod.d[2]
|
||||
spi_pins.cs_n = pmod.d[3:]
|
||||
phy = spi.SPIMaster(spi_pins)
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(
|
||||
|
|
Loading…
Reference in New Issue