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gateware.pipistrello: use pmod for spi

This commit is contained in:
Robert Jördens 2016-02-27 11:29:40 +01:00
parent e7146cc999
commit ade3eda19a
1 changed files with 8 additions and 11 deletions
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19
artiq/gateware/targets/pipistrello.py
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@ -152,8 +152,8 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512, rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512,
ofifo_depth=4)) ofifo_depth=4))
# the last five ttls are used for SPI and a ClockGen # the last TTL is used for ClockGen
for i in range(11): for i in range(15):
if i in (0, 1): if i in (0, 1):
phy = ttl_serdes_spartan6.Output_4X(platform.request("ttl", i), phy = ttl_serdes_spartan6.Output_4X(platform.request("ttl", i),
self.rtio_crg.rtiox4_stb) self.rtio_crg.rtiox4_stb)
@ -192,15 +192,12 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
ofifo_depth=512, ofifo_depth=512,
ififo_depth=4)) ififo_depth=4))
spi_pins = Record([("cs_n", 1), ("clk", 1), ("mosi", 1), ("miso", 1)]) pmod = self.platform.request("pmod", 0)
# cs_n can be multiple bits wide, one-hot spi_pins = Module()
# absence of miso indicates bidirectional mosi spi_pins.clk = pmod.d[0]
self.comb += [ spi_pins.mosi = pmod.d[1]
platform.request("ttl", 11).eq(spi_pins.cs_n), spi_pins.miso = pmod.d[2]
platform.request("ttl", 12).eq(spi_pins.clk), spi_pins.cs_n = pmod.d[3:]
platform.request("ttl", 13).eq(spi_pins.mosi),
spi_pins.miso.eq(platform.request("ttl", 14)),
]
phy = spi.SPIMaster(spi_pins) phy = spi.SPIMaster(spi_pins)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy( rtio_channels.append(rtio.Channel.from_phy(