mirror of https://github.com/m-labs/artiq.git
spi: RTIO_SPI_CHANNEL -> RTIO_FIRST_SPI_CHANNEL
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@ -259,7 +259,7 @@ class NIST_CLOCK(_NIST_Ions):
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phy = spi.SPIMaster(spi_pins)
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self.submodules += phy
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self.config["RTIO_SPI_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=4, ififo_depth=4))
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@ -200,7 +200,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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spi_pins.cs_n = pmod.d[3:]
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phy = spi.SPIMaster(spi_pins)
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self.submodules += phy
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self.config["RTIO_SPI_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=4, ififo_depth=4))
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@ -12,7 +12,7 @@
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void spi_write(long long int timestamp, int channel, int addr,
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unsigned int data)
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{
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rtio_chan_sel_write(CONFIG_RTIO_SPI_CHANNEL + channel);
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rtio_chan_sel_write(CONFIG_RTIO_FIRST_SPI_CHANNEL + channel);
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rtio_o_address_write(addr);
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rtio_o_data_write(data);
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rtio_o_timestamp_write(timestamp);
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