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spi: RTIO_SPI_CHANNEL -> RTIO_FIRST_SPI_CHANNEL

This commit is contained in:
Robert Jördens 2016-02-29 11:35:49 +01:00
parent 5480099f1b
commit ad34927b0a
3 changed files with 3 additions and 3 deletions
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2
artiq/gateware/targets/kc705.py
View File

@ -259,7 +259,7 @@ class NIST_CLOCK(_NIST_Ions):
phy = spi.SPIMaster(spi_pins)
self.submodules += phy
self.config["RTIO_SPI_CHANNEL"] = len(rtio_channels)
self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=4, ififo_depth=4))

2
artiq/gateware/targets/pipistrello.py
View File

@ -200,7 +200,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
spi_pins.cs_n = pmod.d[3:]
phy = spi.SPIMaster(spi_pins)
self.submodules += phy
self.config["RTIO_SPI_CHANNEL"] = len(rtio_channels)
self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=4, ififo_depth=4))

2
artiq/runtime/spi.c
View File

@ -12,7 +12,7 @@
void spi_write(long long int timestamp, int channel, int addr,
unsigned int data)
{
rtio_chan_sel_write(CONFIG_RTIO_SPI_CHANNEL + channel);
rtio_chan_sel_write(CONFIG_RTIO_FIRST_SPI_CHANNEL + channel);
rtio_o_address_write(addr);
rtio_o_data_write(data);
rtio_o_timestamp_write(timestamp);