M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 19:28:26 +08:00
Code Issues Projects Releases Wiki Activity

libboard/ad9154: small cleanup

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2017-11-30 11:33:58 +08:00
parent bd75954192
commit ad2a32d381
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
artiq/firmware/libboard/ad9154.rs
View File

@ -376,7 +376,7 @@ fn dac_setup(linerate: u64) -> Result<(), &'static str> {
0*ad9154_reg::SYNCCLRLAST);
clock::spin_us(1000); // ensure at least one sysref edge
if read(ad9154_reg::SYNC_STATUS) & ad9154_reg::SYNC_LOCK == 0 {
return Err("A9154 no sync lock");
return Err("AD9154 no sync lock");
}
write(ad9154_reg::XBAR_LN_0_1,
0*ad9154_reg::LOGICAL_LANE0_SRC | 1*ad9154_reg::LOGICAL_LANE1_SRC);
@ -478,10 +478,10 @@ pub fn init() -> Result<(), &'static str> {
// Release the JESD clock domain reset late, as we need to
// set up clock chips before.
jesd_unreset();
//for dacno in 0..csr::AD9154.len() {
for dacno in 0..csr::AD9154.len() {
let dacno = dacno as u8;
debug!("setting up A9154-{} DAC...", dacno);
debug!("setting up AD9154-{} DAC...", dacno);
dac_cfg(dacno)?;
}
Ok(())