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Sayma RTM: hold hmc7043 in reset/mute state during init.

This commit is contained in:
Thomas Harty 2018-06-04 13:59:08 +01:00 committed by Sébastien Bourdeauducq
parent b82158a2de
commit ac5c4913ec
2 changed files with 22 additions and 12 deletions
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23
artiq/firmware/libboard_artiq/hmc830_7043.rs
View File

@ -224,10 +224,17 @@ pub mod hmc7043 {
Ok(()) Ok(())
} }
pub fn shutdown() -> Result<(), &'static str> { pub fn enable() -> Result<(), &'static str> {
info!("enabling hmc7043");
unsafe {
csr::crg::hmc7043_rst_write(0);
}
spi_setup(); spi_setup();
info!("shutting down"); write(0x0, 0x1); // Software reset
write(0x1, 0x1); // Sleep mode write(0x0, 0x0); // Normal operation
write(0x1, 0x48); // mute all outputs
Ok(()) Ok(())
} }
@ -236,10 +243,6 @@ pub mod hmc7043 {
spi_setup(); spi_setup();
info!("loading configuration..."); info!("loading configuration...");
write(0x0, 0x1); // Software reset
write(0x0, 0x0);
write(0x1, 0x40); // Enable high-performace/low-noise mode
write(0x3, 0x10); // Disable SYSREF timer write(0x3, 0x10); // Disable SYSREF timer
write(0xA, 0x06); // Disable the REFSYNCIN input write(0xA, 0x06); // Disable the REFSYNCIN input
write(0xB, 0x07); // Enable the CLKIN input as LVPECL write(0xB, 0x07); // Enable the CLKIN input as LVPECL
@ -276,6 +279,7 @@ pub mod hmc7043 {
write(channel_base + 0x8, 0x08) write(channel_base + 0x8, 0x08)
} }
write(0x1, 0x40); // Unmute, high-performace/low-noise mode
info!(" ...done"); info!(" ...done");
Ok(()) Ok(())
@ -305,8 +309,9 @@ pub fn init() -> Result<(), &'static str> {
/* do not use other SPI devices before HMC830 SPI mode selection */ /* do not use other SPI devices before HMC830 SPI mode selection */
hmc830::select_spi_mode(); hmc830::select_spi_mode();
hmc830::detect()?; hmc830::detect()?;
hmc7043::detect()?;
hmc7043::shutdown()?;
hmc830::init()?; hmc830::init()?;
hmc7043::enable()?;
hmc7043::detect()?;
hmc7043::init() hmc7043::init()
} }

11
artiq/gateware/targets/sayma_rtm.py
View File

@ -19,8 +19,11 @@ from artiq.gateware import serwb
from artiq import __version__ as artiq_version from artiq import __version__ as artiq_version
class CRG(Module): class CRG(Module, AutoCSR):
def __init__(self, platform): def __init__(self, platform):
self.hmc7043_rst = CSRStorage(reset=1)
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_clk200 = ClockDomain()
@ -31,7 +34,7 @@ class CRG(Module):
serwb_refclk_bufr = Signal() serwb_refclk_bufr = Signal()
serwb_refclk_bufg = Signal() serwb_refclk_bufg = Signal()
self.specials += Instance("BUFR", i_I=self.serwb_refclk, o_O=serwb_refclk_bufr) self.specials += Instance("BUFR", i_I=self.serwb_refclk, o_O=serwb_refclk_bufr)
self.specials += Instance("BUFG", i_I=serwb_refclk_bufr, o_O=serwb_refclk_bufg) self.specials += Instance("BUFG", i_I=serwb_refclk_bufr, o_O=serwb_refclk_bufg)
pll_locked = Signal() pll_locked = Signal()
pll_fb = Signal() pll_fb = Signal()
@ -110,6 +113,8 @@ class SaymaRTM(Module):
csr_devices = [] csr_devices = []
self.submodules.crg = CRG(platform) self.submodules.crg = CRG(platform)
csr_devices.append("crg")
clk_freq = 125e6 clk_freq = 125e6
self.submodules.rtm_magic = RTMMagic() self.submodules.rtm_magic = RTMMagic()
@ -174,7 +179,7 @@ class SaymaRTM(Module):
platform.request("ad9154_spi", 0), platform.request("ad9154_spi", 0),
platform.request("ad9154_spi", 1))) platform.request("ad9154_spi", 1)))
csr_devices.append("converter_spi") csr_devices.append("converter_spi")
self.comb += platform.request("hmc7043_reset").eq(0) self.comb += platform.request("hmc7043_reset").eq(self.crg.hmc7043_rst.storage)
# AMC/RTM serwb # AMC/RTM serwb
serwb_pads = platform.request("amc_rtm_serwb") serwb_pads = platform.request("amc_rtm_serwb")