diff --git a/artiq/gateware/rtio/cri.py b/artiq/gateware/rtio/cri.py
index bd1e336b3..f3b968d60 100644
--- a/artiq/gateware/rtio/cri.py
+++ b/artiq/gateware/rtio/cri.py
@@ -61,8 +61,6 @@ class Interface(Record):
 class KernelInitiator(Module, AutoCSR):
     def __init__(self, tsc, cri=None):
         self.target = CSRStorage(32)
-        # monotonic, may lag behind the counter in the IO clock domain, but
-        # not be ahead of it.
         self.timestamp = CSRStorage(64)
 
         # Writing timestamp clears o_data. This implements automatic